From 269263eecfbcc5f21647f9675db7a1280f6d6c03 Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Sun, 22 May 2022 21:16:38 -0400
Subject: [PATCH] Implement RTE, RTS, RTR.

---
 .../68000ComparativeTests.mm                  |  4 +-
 .../Implementation/68000Mk2Implementation.hpp | 58 +++++++++++++++++++
 2 files changed, 60 insertions(+), 2 deletions(-)

diff --git a/OSBindings/Mac/Clock SignalTests/68000ComparativeTests.mm b/OSBindings/Mac/Clock SignalTests/68000ComparativeTests.mm
index d38db094c..8d23e147d 100644
--- a/OSBindings/Mac/Clock SignalTests/68000ComparativeTests.mm	
+++ b/OSBindings/Mac/Clock SignalTests/68000ComparativeTests.mm	
@@ -184,8 +184,8 @@ struct TestProcessor: public CPU::MC68000Mk2::BusHandler {
 		@"nbcd_pea.json",
 		@"neg_not.json",
 		@"negx_clr.json",
-//		@"rtr.json",
-//		@"rts.json",
+		@"rtr.json",
+		@"rts.json",
 		@"swap.json",
 		@"tas.json",
 		@"tst.json",
diff --git a/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp b/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
index 1284e712b..ac1dc637c 100644
--- a/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
+++ b/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
@@ -167,6 +167,9 @@ enum ExecutionState: int {
 	PEA,
 	TAS,
 	MOVEtoCCRSR,
+	RTR,
+	RTE,
+	RTS,
 };
 
 // MARK: - The state machine.
@@ -742,6 +745,10 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 					MoveToStateSpecific(CalcEffectiveAddress);
 				});
 
+				StdCASE(RTR, MoveToStateSpecific(RTR));
+				StdCASE(RTE, MoveToStateSpecific(RTE));
+				StdCASE(RTS, MoveToStateSpecific(RTS));
+
 				default:
 					assert(false);
 			}
@@ -1988,6 +1995,57 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 			Prefetch();
 		MoveToStateSpecific(Decode);
 
+		//
+		// RTR, RTS, RTE
+		//
+		BeginState(RTS):
+			SetupDataAccess(Microcycle::Read, Microcycle::SelectWord);
+			SetDataAddress(registers_[15].l);
+
+			Access(program_counter_.high);
+			registers_[15].l += 2;
+			Access(program_counter_.low);
+			registers_[15].l += 2;
+
+			Prefetch();
+			Prefetch();
+		MoveToStateSpecific(Decode);
+
+		BeginState(RTE):
+			SetupDataAccess(Microcycle::Read, Microcycle::SelectWord);
+			SetDataAddress(registers_[15].l);
+
+			Access(program_counter_.high);
+			registers_[15].l += 2;
+			Access(program_counter_.low);
+			registers_[15].l += 2;
+
+			Access(temporary_value_.low);
+			registers_[15].l += 2;
+			status_.set_status(temporary_value_.w);
+
+			Prefetch();
+			Prefetch();
+		MoveToStateSpecific(Decode);
+
+		BeginState(RTR):
+			SetupDataAccess(Microcycle::Read, Microcycle::SelectWord);
+			SetDataAddress(registers_[15].l);
+
+			registers_[15].l += 2;
+			Access(program_counter_.high);
+			registers_[15].l += 2;
+			Access(program_counter_.low);
+
+			registers_[15].l -= 4;
+			Access(temporary_value_.low);
+			registers_[15].l += 6;
+			status_.set_ccr(temporary_value_.w);
+
+			Prefetch();
+			Prefetch();
+		MoveToStateSpecific(Decode);
+
 		//
 		// Various states TODO.
 		//