Permitted register 3 to dictate vertical sync length.

2026-04-19 19:16:34 +00:00 · 2017-08-04 08:56:36 -04:00
parent d9097facf1
commit 26ce6cdab2
1 changed files with 2 additions and 1 deletions
@@ -106,7 +106,8 @@ template <class T> class CRTC6845 {
 							// check for start of vertical sync
 							if(line_counter_ == registers_[7]) {
 								bus_state_.vsync = true;
-								vsync_down_counter_ = 16;	// TODO
+								vsync_down_counter_ = registers_[3] >> 4;
+								if(!vsync_down_counter_) vsync_down_counter_ = 16;
 							}

 							// check for entry into the overflow area