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https://github.com/TomHarte/CLK.git
synced 2026-04-24 05:18:36 +00:00
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+36
-1
@@ -25,9 +25,44 @@ bool Bus::clock() {
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}
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void Bus::set_clock_data(bool clock_pulled, bool data_pulled) {
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// TODO: all intelligence.
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const bool has_new_bit = clock_pulled && !clock_;
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clock_ = clock_pulled;
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data_ = data_pulled;
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// TODO: "Stop condition: SDA goes high after SCL (?)".
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if(has_new_bit) {
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// Test for a start bit.
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//
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// "Start condition: SDA goes low before SCL".
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if(input_count_ < 0 && data_) {
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input_count_ = 0;
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}
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// Accumulate if started.
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if(input_count_ >= 0) {
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input_ = uint16_t((input_ << 1) | (data_pulled ? 0 : 1));
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++input_count_;
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}
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// Test for meaning.
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switch(phase_) {
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case Phase::AwaitingAddress:
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if(input_count_ == 9) {
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printf("Calling %02x?", uint8_t(input_));
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auto pair = peripherals_.find(uint8_t(input_));
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if(pair != peripherals_.end()) {
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active_peripheral_ = pair->second;
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// TODO: device found; pull data low for the next clock.
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}
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}
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break;
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case Phase::CollectingData:
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break;
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}
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}
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}
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void Bus::add_peripheral(Peripheral *peripheral, int address) {
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