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Resolve video addressing issues.
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3f40e409c5
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@ -79,7 +79,7 @@ struct MemoryController {
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switch(write_zones_[(address >> 21) & 31]) {
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case Zone::DMAAndMEMC: {
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const auto buffer_address = [](uint32_t source) -> uint32_t {
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return (source & 0x1fffc0) << 2;
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return (source & 0x1'fffc) << 2;
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};
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// The MEMC itself isn't on the data bus; all values below should be taken from `address`.
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@ -126,8 +126,6 @@ struct Video {
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if(vertical_state_.position == vertical_timing_.period) {
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vertical_state_.position = 0;
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address_ = frame_start_;
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if(address_ == buffer_end_) address_ = buffer_start_;
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entered_sync_ = true;
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interrupt_observer_.update_interrupts();
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}
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@ -157,7 +155,12 @@ struct Video {
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const auto next_byte = [&]() -> uint8_t {
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const auto next = ram_[address_];
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++address_;
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if(address_ == buffer_end_) address_ = buffer_start_;
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// `buffer_end_` is the final address that a 16-byte block will be fetched from;
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// the +16 here papers over the fact that I'm not accurately implementing DMA.
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if(address_ == buffer_end_ + 16) {
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address_ = buffer_start_;
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}
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return next;
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};
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@ -284,10 +287,10 @@ struct Video {
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return interrupt;
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}
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void set_frame_start(uint32_t address) { frame_start_ = address & 0x7'ffff; }
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void set_buffer_start(uint32_t address) { buffer_start_ = address & 0x7'ffff; }
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void set_buffer_end(uint32_t address) { buffer_end_ = address & 0x7'ffff; }
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void set_cursor_start(uint32_t address) { cursor_start_ = address & 0x7'ffff; }
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void set_frame_start(uint32_t address) { frame_start_ = address; }
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void set_buffer_start(uint32_t address) { buffer_start_ = address; }
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void set_buffer_end(uint32_t address) { buffer_end_ = address; }
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void set_cursor_start(uint32_t address) { cursor_start_ = address; }
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Outputs::CRT::CRT &crt() { return crt_; }
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const Outputs::CRT::CRT &crt() const { return crt_; }
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