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Eliminate redundant [space][tab] pairs.

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This commit is contained in:
Thomas Harte 2023-05-12 14:14:45 -04:00
parent 60bec3d4c0
commit 28c79b2885
54 changed files with 198 additions and 198 deletions
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4
Analyser/Static/Commodore/StaticAnalyser.cpp
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@ -188,8 +188,8 @@ Analyser::Static::TargetList Analyser::Static::Commodore::GetTargets(const Media
// Unhandled:
//
// M6: this is a C64 file.
// MV: this is a Vic-20 file.
// M6: this is a C64 file.
// MV: this is a Vic-20 file.
// J1/J2: this C64 file should have the primary joystick in slot 1/2.
// RO: this disk image should be treated as read-only.
}

2
Analyser/Static/StaticAnalyser.cpp
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@ -244,7 +244,7 @@ TargetList Analyser::Static::GetTargets(const std::string &file_name) {
const std::string extension = get_extension(file_name);
// Check whether the file directly identifies a target; if so then just return that.
#define Format(ext, class) \
#define Format(ext, class) \
if(extension == ext) { \
try { \
auto target = Storage::State::class::load(file_name); \

2
ClockReceiver/JustInTime.hpp
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@ -294,7 +294,7 @@ template <class T, class LocalTimeScale = HalfCycles, class TargetTimeScale = Lo
/// Constructs a new AsyncJustInTimeActor using the same construction arguments as the included object.
template<typename... Args> AsyncJustInTimeActor(TargetTimeScale threshold, Args&&... args) :
object_(std::forward<Args>(args)...),
threshold_(threshold) {}
threshold_(threshold) {}
/// Adds time to the actor.
inline void operator += (const LocalTimeScale &rhs) {

2
Components/1770/1770.cpp
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@ -66,7 +66,7 @@ uint8_t WD1770::read(int address) {
// Per Jean Louis-Guérin's documentation:
//
// * the write-protect bit is locked into place by a type 2 or type 3 command, but is
// * the write-protect bit is locked into place by a type 2 or type 3 command, but is
// read live after a type 1.
// * the track 0 bit is captured during a type 1 instruction and lost upon any other type,
// it is not live sampled.

8
Components/6522/Implementation/6522Implementation.hpp
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@ -271,7 +271,7 @@ template <typename T> void MOS6522<T>::set_control_line_input(Port port, Line li
// TODO: and at least one full clock since the shift register was written?
if(port == Port::B) {
switch(shift_mode()) {
default: break;
default: break;
case ShiftMode::InUnderCB1: if(value) shift_in(); break; // Shifts in are captured on a low-to-high transition.
case ShiftMode::OutUnderCB1: if(!value) shift_out(); break; // Shifts out are updated on a high-to-low transition.
}
@ -329,7 +329,7 @@ template <typename T> void MOS6522<T>::do_phase2() {
// If the shift register is shifting according to the input clock, do a shift.
switch(shift_mode()) {
default: break;
default: break;
case ShiftMode::InUnderPhase2: shift_in(); break;
case ShiftMode::OutUnderPhase2: shift_out(); break;
}
@ -345,9 +345,9 @@ template <typename T> void MOS6522<T>::do_phase1() {
// If the shift register is shifting according to this timer, do a shift.
// TODO: "shift register is driven by only the low order 8 bits of timer 2"?
switch(shift_mode()) {
default: break;
default: break;
case ShiftMode::InUnderT2: shift_in(); break;
case ShiftMode::OutUnderT2FreeRunning: shift_out(); break;
case ShiftMode::OutUnderT2FreeRunning: shift_out(); break;
case ShiftMode::OutUnderT2: shift_out(); break; // TODO: present a clock on CB1.
}

8
Components/6560/6560.hpp
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@ -83,11 +83,11 @@ template <class BusHandler> class MOS6560 {
speaker_.set_input_rate(float(clock_rate / 4.0));
}
void set_scan_target(Outputs::Display::ScanTarget *scan_target) { crt_.set_scan_target(scan_target); }
void set_scan_target(Outputs::Display::ScanTarget *scan_target) { crt_.set_scan_target(scan_target); }
Outputs::Display::ScanStatus get_scaled_scan_status() const { return crt_.get_scaled_scan_status() / 4.0f; }
void set_display_type(Outputs::Display::DisplayType display_type) { crt_.set_display_type(display_type); }
Outputs::Display::DisplayType get_display_type() const { return crt_.get_display_type(); }
Outputs::Speaker::Speaker *get_speaker() { return &speaker_; }
void set_display_type(Outputs::Display::DisplayType display_type) { crt_.set_display_type(display_type); }
Outputs::Display::DisplayType get_display_type() const { return crt_.get_display_type(); }
Outputs::Speaker::Speaker *get_speaker() { return &speaker_; }
void set_high_frequency_cutoff(float cutoff) {
speaker_.set_high_frequency_cutoff(cutoff);

2
Components/9918/Implementation/9918.cpp
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@ -957,7 +957,7 @@ void Base<personality>::commit_register(int reg, uint8_t value) {
switch(value >> 4) {
// All codes not listed below are invalid; treat them as STOP.
default:
case 0b0000: Storage<personality>::command_ = nullptr; break; // STOP.
case 0b0000: Storage<personality>::command_ = nullptr; break; // STOP.
case 0b0100: Begin(Point<true>); break; // POINT [read a pixel colour].
case 0b0101: Begin(Point<false>); break; // PSET [plot a pixel].

2
Components/9918/Implementation/9918Base.hpp
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@ -585,7 +585,7 @@ template <Personality personality> struct Base: public Storage<personality> {
/// Helper for TMS dispatches; contains a switch statement with cases 0 to 170, each of the form:
///
/// if constexpr (use_end && end == n) return; [[fallthrough]]; case n: fetcher.fetch<n>();
/// if constexpr (use_end && end == n) return; [[fallthrough]]; case n: fetcher.fetch<n>();
///
/// i.e. it provides standard glue to enter a fetch sequence at any point, while the fetches themselves are templated on the cycle
/// at which they appear for neater expression.

4
Components/9918/Implementation/ClockConverter.hpp
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@ -161,7 +161,7 @@ template <Personality personality> struct LineLayout<personality, std::enable_if
constexpr static int EndOfPixels = 319;
constexpr static int EndOfRightBorder = 334;
constexpr static int CyclesPerLine = 342;
constexpr static int CyclesPerLine = 342;
constexpr static int TextModeEndOfLeftBorder = 69;
constexpr static int TextModeEndOfPixels = 309;
@ -180,7 +180,7 @@ template <Personality personality> struct LineLayout<personality, std::enable_if
constexpr static int EndOfPixels = 1282;
constexpr static int EndOfRightBorder = 1341;
constexpr static int CyclesPerLine = 1368;
constexpr static int CyclesPerLine = 1368;
constexpr static int TextModeEndOfLeftBorder = 294;
constexpr static int TextModeEndOfPixels = 1254;

6
Components/9918/Implementation/Storage.hpp
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@ -167,7 +167,7 @@ struct YamahaFetcher {
case 1338: return Event(Event::Type::SpritePattern, 2);
case 34: return Event(Event::Type::SpritePattern, 4);
case 98: return Event(Event::Type::SpritePattern, 6);
case 1264: case 1330: case 28: case 92:
case 1264: case 1330: case 28: case 92:
return Event::Type::External;
}
}
@ -281,8 +281,8 @@ struct YamahaFetcher {
const int sub_block = offset & 31;
switch(sub_block) {
case 0: if(block > 0) return Event(Event::Type::Name, uint8_t(block - 1));
case 6: if((sub_block & 3) != 3) return Event::Type::External;
case 12: if(block < 32) return Event(Event::Type::SpriteY, uint8_t(block));
case 6: if((sub_block & 3) != 3) return Event::Type::External;
case 12: if(block < 32) return Event(Event::Type::SpriteY, uint8_t(block));
case 18: if(block > 0) return Event(Event::Type::Pattern, uint8_t(block - 1));
case 24: if(block > 0) return Event(Event::Type::Colour, uint8_t(block - 1));
}

2
Components/AppleClock/AppleClock.hpp
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@ -195,7 +195,7 @@ class SerialClock: public ClockStorage {
Sets the current clock and data inputs to the clock.
*/
void set_input(bool clock, bool data) {
// The data line is valid when the clock transitions to level 0.
// The data line is valid when the clock transitions to level 0.
if(clock && !previous_clock_) {
// Shift into the command_ register, no matter what.
command_ = uint16_t((command_ << 1) | (data ? 1 : 0));

4
InstructionSets/6809/OperationMapper.hpp
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@ -100,7 +100,7 @@ template <int i, typename SchedulerT> void OperationMapper<Page::Page0>::dispatc
AM::Variant, AM::Variant, AM::Inherent, AM::Inherent,
AM::Illegal, AM::Illegal, AM::Relative, AM::Relative,
AM::Illegal, AM::Inherent, AM::Immediate, AM::Illegal,
AM::Immediate, AM::Inherent, AM::Inherent, AM::Inherent,
AM::Immediate, AM::Inherent, AM::Inherent, AM::Inherent,
};
s.template schedule<operations[lower], modes[lower]>();
} break;
@ -162,7 +162,7 @@ template <int i, typename SchedulerT> void OperationMapper<Page::Page0>::dispatc
O::EORA, O::ADCA, O::ORA, O::ADDA, O::CMPX, O::JSR, O::LDX, O::STX,
};
if(i == 0x8d) s.template schedule<O::BSR, AM::Relative>();
else s.template schedule<operations[lower], mode>();
else s.template schedule<operations[lower], mode>();
} break;
case 0xc: case 0xd: case 0xe: case 0xf: {
constexpr Operation operations[] = {

6
InstructionSets/M50740/Instruction.hpp
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@ -65,7 +65,7 @@ enum class Operation: uint8_t {
INX, INY, DEX, DEY,
FST, SLW,
NOP,
PHA, PHP, PLA, PLP,
PHA, PHP, PLA, PLP,
STP,
TAX, TAY, TSX, TXA,
TXS, TYA,
@ -120,7 +120,7 @@ inline constexpr const char *operation_name(Operation operation) {
MAP(BCC); MAP(BCS); MAP(BEQ); MAP(BMI); MAP(BNE); MAP(BPL); MAP(BVC); MAP(BVS);
MAP(BRA); MAP(BRK); MAP(JMP); MAP(JSR); MAP(RTI); MAP(RTS); MAP(CLC); MAP(CLD);
MAP(CLI); MAP(CLT); MAP(CLV); MAP(SEC); MAP(SED); MAP(SEI); MAP(SET); MAP(INX);
MAP(INY); MAP(DEX); MAP(DEY); MAP(FST); MAP(SLW); MAP(NOP); MAP(PHA); MAP(PHP);
MAP(INY); MAP(DEX); MAP(DEY); MAP(FST); MAP(SLW); MAP(NOP); MAP(PHA); MAP(PHP);
MAP(PLA); MAP(PLP); MAP(STP); MAP(TAX); MAP(TAY); MAP(TSX); MAP(TXA); MAP(TXS);
MAP(TYA); MAP(ADC); MAP(SBC); MAP(AND); MAP(ORA); MAP(EOR); MAP(BIT); MAP(CMP);
MAP(CPX); MAP(CPY); MAP(LDA); MAP(LDX); MAP(LDY); MAP(TST); MAP(ASL); MAP(LSR);
@ -185,7 +185,7 @@ inline std::string address(AddressingMode addressing_mode, const uint8_t *operat
#define NUM(x) std::setfill('0') << std::setw(2) << int(x)
#define NUM4(x) std::setfill('0') << std::setw(4) << int(x)
switch(addressing_mode) {
default: return "???";
default: return "???";
case AddressingMode::Implied: return "";
case AddressingMode::Accumulator: return "A ";
case AddressingMode::Immediate: output << "#$" << NUM(operation[1]); break;

12
InstructionSets/M68k/Decoder.cpp
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@ -26,7 +26,7 @@ constexpr AddressingMode extended_modes[] = {
};
/// @returns The @c AddressingMode given the specified mode and reg, subject to potential
/// aliasing on the '020+ as described above the @c AddressingMode enum.
/// aliasing on the '020+ as described above the @c AddressingMode enum.
constexpr AddressingMode combined_mode(int mode, int reg) {
assert(mode >= 0 && mode < 8);
assert(reg >= 0 && reg < 8);
@ -162,13 +162,13 @@ template <typename Predecoder<model>::OpT op> uint32_t Predecoder<model>::invali
//
// All modes: the complete set (other than Quick).
//
static constexpr auto AllModes = Dn | An | Ind | PostInc | PreDec | d16An | d8AnXn | XXXw | XXXl | Imm | d16PC | d8PCXn;
static constexpr auto AllModesNoAn = AllModes & ~An;
static constexpr auto AllModes = Dn | An | Ind | PostInc | PreDec | d16An | d8AnXn | XXXw | XXXl | Imm | d16PC | d8PCXn;
static constexpr auto AllModesNoAn = AllModes & ~An;
//
// Alterable addressing modes (with and without AddressRegisterDirect).
//
static constexpr auto AlterableAddressingModes = Dn | An | Ind | PostInc | PreDec | d16An | d8AnXn | XXXw | XXXl;
static constexpr auto AlterableAddressingModes = Dn | An | Ind | PostInc | PreDec | d16An | d8AnXn | XXXw | XXXl;
static constexpr auto AlterableAddressingModesNoAn = AlterableAddressingModes & ~An;
//
@ -224,7 +224,7 @@ template <typename Predecoder<model>::OpT op> uint32_t Predecoder<model>::invali
>::value;
case OpT(Operation::ADDAw): case OpT(Operation::ADDAl):
case OpT(Operation::CMPAw): case OpT(Operation::CMPAl):
case OpT(Operation::CMPAw): case OpT(Operation::CMPAl):
case OpT(Operation::SUBAw): case OpT(Operation::SUBAl):
case OpT(Operation::MOVEAw): case OpT(Operation::MOVEAl):
return ~TwoOperandMask<
@ -728,7 +728,7 @@ template <typename Predecoder<model>::OpT op, bool validate> Preinstruction Pred
// Implicitly: source is an immediate value;
// b0–b2 and b3–b5: destination effective address.
//
case EORIb: case EORIl: case EORIw:
case EORIb: case EORIl: case EORIw:
case ORIb: case ORIl: case ORIw:
case ANDIb: case ANDIl: case ANDIw:
case SUBIb: case SUBIl: case SUBIw:

2
InstructionSets/M68k/Executor.hpp
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@ -21,7 +21,7 @@ namespace InstructionSet::M68k {
/// Maps the 68k function codes such that bits 0, 1 and 2 represent
/// FC0, FC1 and FC2 respectively.
enum class FunctionCode {
UserData = 0b001,
UserData = 0b001,
UserProgram = 0b010,
SupervisorData = 0b101,
SupervisorProgram = 0b110,

2
InstructionSets/M68k/Implementation/ExecutorImplementation.hpp
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@ -238,7 +238,7 @@ uint32_t Executor<model, BusHandler>::State::index_8bitdisplacement(uint32_t bas
// Fetch base displacement.
uint32_t base_displacement = 0;
switch((extension >> 4) & 3) {
default: break;
default: break;
case 2: base_displacement = read_pc<uint16_t>(); break;
case 3: base_displacement = read_pc<uint32_t>(); break;
}

10
InstructionSets/M68k/Implementation/InstructionOperandFlags.hpp
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@ -113,7 +113,7 @@ template <Model model, Operation t_operation> constexpr uint8_t operand_flags(Op
//
// Two-operand; read source, write dest.
//
case Operation::MOVEb: case Operation::MOVEw: case Operation::MOVEl:
case Operation::MOVEb: case Operation::MOVEw: case Operation::MOVEl:
case Operation::MOVEAw: case Operation::MOVEAl:
case Operation::PACK: case Operation::UNPK:
return FetchOp1 | StoreOp2;
@ -122,12 +122,12 @@ template <Model model, Operation t_operation> constexpr uint8_t operand_flags(Op
// Two-operand; read both, write dest.
//
case Operation::ABCD: case Operation::SBCD:
case Operation::ADDb: case Operation::ADDw: case Operation::ADDl:
case Operation::ADDb: case Operation::ADDw: case Operation::ADDl:
case Operation::ADDAw: case Operation::ADDAl:
case Operation::ADDXb: case Operation::ADDXw: case Operation::ADDXl:
case Operation::SUBb: case Operation::SUBw: case Operation::SUBl:
case Operation::ADDXb: case Operation::ADDXw: case Operation::ADDXl:
case Operation::SUBb: case Operation::SUBw: case Operation::SUBl:
case Operation::SUBAw: case Operation::SUBAl:
case Operation::SUBXb: case Operation::SUBXw: case Operation::SUBXl:
case Operation::SUBXb: case Operation::SUBXw: case Operation::SUBXl:
case Operation::ORb: case Operation::ORw: case Operation::ORl:
case Operation::ANDb: case Operation::ANDw: case Operation::ANDl:
case Operation::EORb: case Operation::EORw: case Operation::EORl:

2
InstructionSets/M68k/Implementation/PerformImplementation.hpp
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@ -465,7 +465,7 @@ template <Operation operation, typename IntT, typename FlowController> void rox(
// When shift is zero, extend is unaffected but is copied to carry.
status.carry_flag = status.extend_flag;
} else {
switch(operation) {
switch(operation) {
case Operation::ROXLb: case Operation::ROXLw: case Operation::ROXLl:
status.carry_flag = Status::FlagT((destination >> (size - shift)) & 1);

2
InstructionSets/M68k/Instruction.hpp
View File

@ -83,7 +83,7 @@ enum class Operation: uint8_t {
ANDb, ANDw, ANDl,
EORb, EORw, EORl,
NOTb, NOTw, NOTl,
NOTb, NOTw, NOTl,
ORb, ORw, ORl,
MULUw, MULSw,

2
InstructionSets/M68k/Status.hpp
View File

@ -68,7 +68,7 @@ struct Status {
/// Gets the current condition codes.
constexpr uint16_t ccr() const {
return
(carry_flag ? ConditionCode::Carry : 0) |
(carry_flag ? ConditionCode::Carry : 0) |
(overflow_flag ? ConditionCode::Overflow : 0) |
(!zero_result ? ConditionCode::Zero : 0) |
(negative_flag ? ConditionCode::Negative : 0) |

44
InstructionSets/PowerPC/Instruction.hpp
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@ -46,13 +46,13 @@ enum class BranchOption: uint32_t {
// condition ending Set or Clear => test the condition bit.
Dec_NotZeroAndClear = 0b0000,
Dec_ZeroAndClear = 0b0001,
Clear = 0b0010,
Clear = 0b0010,
Dec_NotZeroAndSet = 0b0100,
Dec_ZeroAndSet = 0b0101,
Set = 0b0110,
Dec_NotZero = 0b1000,
Dec_ZeroAndSet = 0b0101,
Set = 0b0110,
Dec_NotZero = 0b1000,
Dec_Zero = 0b1001,
Always = 0b1010,
Always = 0b1010,
};
@ -1389,30 +1389,30 @@ struct Instruction {
int32_t imm() const { return (opcode >> 12) & 0xf; }
/// Specifies the conditions on which to trap.
int32_t to() const { return (opcode >> 21) & 0x1f; }
int32_t to() const { return (opcode >> 21) & 0x1f; }
/// Register source A or destination.
uint32_t rA() const { return (opcode >> 16) & 0x1f; }
uint32_t rA() const { return (opcode >> 16) & 0x1f; }
/// Register source B.
uint32_t rB() const { return (opcode >> 11) & 0x1f; }
uint32_t rB() const { return (opcode >> 11) & 0x1f; }
/// Register destination.
uint32_t rD() const { return (opcode >> 21) & 0x1f; }
uint32_t rD() const { return (opcode >> 21) & 0x1f; }
/// Register source.
uint32_t rS() const { return (opcode >> 21) & 0x1f; }
uint32_t rS() const { return (opcode >> 21) & 0x1f; }
/// Floating point register source A.
uint32_t frA() const { return (opcode >> 16) & 0x1f; }
uint32_t frA() const { return (opcode >> 16) & 0x1f; }
/// Floating point register source B.
uint32_t frB() const { return (opcode >> 11) & 0x1f; }
uint32_t frB() const { return (opcode >> 11) & 0x1f; }
/// Floating point register source C.
uint32_t frC() const { return (opcode >> 6) & 0x1f; }
uint32_t frC() const { return (opcode >> 6) & 0x1f; }
/// Floating point register source.
uint32_t frS() const { return (opcode >> 21) & 0x1f; }
uint32_t frS() const { return (opcode >> 21) & 0x1f; }
/// Floating point register destination.
uint32_t frD() const { return (opcode >> 21) & 0x1f; }
uint32_t frD() const { return (opcode >> 21) & 0x1f; }
/// Branch conditional options as per PowerPC spec, i.e. options + branch-prediction flag.
uint32_t bo() const { return (opcode >> 21) & 0x1f; }
uint32_t bo() const { return (opcode >> 21) & 0x1f; }
/// Just the branch options, with the branch prediction flag severed.
BranchOption branch_options() const {
return BranchOption((opcode >> 22) & 0xf);
@ -1422,7 +1422,7 @@ struct Instruction {
return opcode & 0x200000;
}
/// Source condition register bit for branch conditionals.
uint32_t bi() const { return (opcode >> 16) & 0x1f; }
uint32_t bi() const { return (opcode >> 16) & 0x1f; }
/// Branch displacement; provided as already sign extended.
int16_t bd() const { return int16_t(opcode & 0xfffc); }
@ -1447,9 +1447,9 @@ struct Instruction {
/// Provides the mask described by 32-bit rotate operations.
///
/// Per IBM's rules:
/// mb < me+1 => set [mb, me]
/// mb == me+1 => set all bits
/// mb > me+1 => complement of set [me+1, mb-1]
/// mb < me+1 => set [mb, me]
/// mb == me+1 => set all bits
/// mb > me+1 => complement of set [me+1, mb-1]
template <typename IntT> IntT rotate_mask() const {
const auto mb_bit = mb();
const auto me_bit = me();
@ -1521,9 +1521,9 @@ struct Instruction {
/// Identifies a special purpose register.
uint32_t spr() const { return (opcode >> 11) & 0x3ff; }
uint32_t spr() const { return (opcode >> 11) & 0x3ff; }
/// Identifies a time base register.
uint32_t tbr() const { return (opcode >> 11) & 0x3ff; }
uint32_t tbr() const { return (opcode >> 11) & 0x3ff; }
};
// Sanity check on Instruction size.

8
InstructionSets/x86/DataPointerResolver.hpp
View File

@ -202,12 +202,12 @@ template <typename DataT> void DataPointerResolver<model, RegistersT, MemoryT>::
} \
break;
#define ALLREGS(v, i) rw(v, eAX, i); rw(v, eCX, i); \
rw(v, eDX, i); rw(v, eBX, i); \
#define ALLREGS(v, i) rw(v, eAX, i); rw(v, eCX, i); \
rw(v, eDX, i); rw(v, eBX, i); \
rw(v, eSPorAH, i); rw(v, eBPorCH, i); \
rw(v, eSIorDH, i); rw(v, eDIorBH, i); \
rw(v, ES, i); rw(v, CS, i); \
rw(v, SS, i); rw(v, DS, i); \
rw(v, ES, i); rw(v, CS, i); \
rw(v, SS, i); rw(v, DS, i); \
rw(v, FS, i); rw(v, GS, i);
template <Model model, typename RegistersT, typename MemoryT>

58
InstructionSets/x86/Decoder.cpp
View File

@ -691,13 +691,13 @@ std::pair<int, typename Decoder<model>::InstructionT> Decoder<model>::decode(con
switch(reg) {
default: undefined();
case 0: operation_ = Operation::TEST; break;
case 2: operation_ = Operation::NOT; break;
case 3: operation_ = Operation::NEG; break;
case 4: operation_ = Operation::MUL; break;
case 5: operation_ = Operation::IMUL_1; break;
case 6: operation_ = Operation::DIV; break;
case 7: operation_ = Operation::IDIV; break;
case 0: operation_ = Operation::TEST; break;
case 2: operation_ = Operation::NOT; break;
case 3: operation_ = Operation::NEG; break;
case 4: operation_ = Operation::MUL; break;
case 5: operation_ = Operation::IMUL_1; break;
case 6: operation_ = Operation::DIV; break;
case 7: operation_ = Operation::IDIV; break;
}
break;
@ -729,15 +729,15 @@ std::pair<int, typename Decoder<model>::InstructionT> Decoder<model>::decode(con
destination_ = memreg;
switch(reg) {
default: undefined();
default: undefined();
case 0: operation_ = Operation::ROL; break;
case 1: operation_ = Operation::ROR; break;
case 2: operation_ = Operation::RCL; break;
case 3: operation_ = Operation::RCR; break;
case 4: operation_ = Operation::SAL; break;
case 5: operation_ = Operation::SHR; break;
case 7: operation_ = Operation::SAR; break;
case 0: operation_ = Operation::ROL; break;
case 1: operation_ = Operation::ROR; break;
case 2: operation_ = Operation::RCL; break;
case 3: operation_ = Operation::RCR; break;
case 4: operation_ = Operation::SAL; break;
case 5: operation_ = Operation::SHR; break;
case 7: operation_ = Operation::SAR; break;
}
break;
@ -745,7 +745,7 @@ std::pair<int, typename Decoder<model>::InstructionT> Decoder<model>::decode(con
source_ = destination_ = memreg;
switch(reg) {
default: undefined();
default: undefined();
case 0: operation_ = Operation::INC; break;
case 1: operation_ = Operation::DEC; break;
@ -756,7 +756,7 @@ std::pair<int, typename Decoder<model>::InstructionT> Decoder<model>::decode(con
source_ = destination_ = memreg;
switch(reg) {
default: undefined();
default: undefined();
case 0: operation_ = Operation::INC; break;
case 1: operation_ = Operation::DEC; break;
@ -807,12 +807,12 @@ std::pair<int, typename Decoder<model>::InstructionT> Decoder<model>::decode(con
switch(reg) {
default: undefined();
case 0: operation_ = Operation::SLDT; break;
case 1: operation_ = Operation::STR; break;
case 2: operation_ = Operation::LLDT; break;
case 3: operation_ = Operation::LTR; break;
case 4: operation_ = Operation::VERR; break;
case 5: operation_ = Operation::VERW; break;
case 0: operation_ = Operation::SLDT; break;
case 1: operation_ = Operation::STR; break;
case 2: operation_ = Operation::LLDT; break;
case 3: operation_ = Operation::LTR; break;
case 4: operation_ = Operation::VERR; break;
case 5: operation_ = Operation::VERW; break;
}
break;
@ -822,12 +822,12 @@ std::pair<int, typename Decoder<model>::InstructionT> Decoder<model>::decode(con
switch(reg) {
default: undefined();
case 0: operation_ = Operation::SGDT; break;
case 1: operation_ = Operation::SIDT; break;
case 2: operation_ = Operation::LGDT; break;
case 3: operation_ = Operation::LIDT; break;
case 4: operation_ = Operation::SMSW; break;
case 6: operation_ = Operation::LMSW; break;
case 0: operation_ = Operation::SGDT; break;
case 1: operation_ = Operation::SIDT; break;
case 2: operation_ = Operation::LGDT; break;
case 3: operation_ = Operation::LIDT; break;
case 4: operation_ = Operation::SMSW; break;
case 6: operation_ = Operation::LMSW; break;
}
break;

6
Machines/Amiga/Bitplanes.hpp
View File

@ -78,9 +78,9 @@ class BitplaneShifter {
/// The value is arranges so that MSB = first pixel to output, LSB = last.
///
/// Each byte is swizzled to provide easier playfield separation, being in the form:
/// b6, b7 = 0;
/// b3–b5: planes 1, 3 and 5;
/// b0–b2: planes 0, 2 and 4.
/// b6, b7 = 0;
/// b3–b5: planes 1, 3 and 5;
/// b0–b2: planes 0, 2 and 4.
uint32_t get(bool high_res) {
if(high_res) {
return uint32_t(data_[1] >> 32);

14
Machines/Amiga/Chipset.cpp
View File

@ -393,9 +393,9 @@ template <int cycle> void Chipset::output() {
constexpr int end_of_pixels = 15;
constexpr int blank1 = 3 + end_of_pixels;
constexpr int sync = 17 + blank1;
constexpr int blank2 = 3 + sync;
constexpr int burst = 9 + blank2;
constexpr int blank3 = 6 + burst;
constexpr int blank2 = 3 + sync;
constexpr int burst = 9 + blank2;
constexpr int blank3 = 6 + burst;
static_assert(blank3 == 53);
#define LINK(location, action, length) \
@ -674,8 +674,8 @@ template <bool stop_on_cpu> int Chipset::advance_slots(int first_slot, int last_
}
assert(last_slot > first_slot);
#define C(x) \
case x: \
#define C(x) \
case x: \
output<x>(); \
\
if constexpr (stop_on_cpu) { \
@ -683,8 +683,8 @@ template <bool stop_on_cpu> int Chipset::advance_slots(int first_slot, int last_
return 1 + x - first_slot; \
} \
} else { \
perform_cycle<x, stop_on_cpu>(); \
} \
perform_cycle<x, stop_on_cpu>(); \
} \
\
if((x + 1) == last_slot) break; \
[[fallthrough]]

2
Machines/Apple/ADB/Bus.hpp
View File

@ -47,7 +47,7 @@ inline std::ostream &operator <<(std::ostream &stream, Command::Type type) {
case Command::Type::Flush: stream << "flush"; break;
case Command::Type::Listen: stream << "listen"; break;
case Command::Type::Talk: stream << "talk"; break;
default: stream << "reserved"; break;
default: stream << "reserved"; break;
}
return stream;
}

2
Machines/Apple/ADB/Keyboard.cpp
View File

@ -161,7 +161,7 @@ uint16_t KeyboardMapper::mapped_key_for_key(Inputs::Keyboard::Key key) const {
switch(key) {
default: return MachineTypes::MappedKeyboardMachine::KeyNotMapped;
#define Bind(x, y) case Key::x: return uint16_t(ADBKey::y)
#define Bind(x, y) case Key::x: return uint16_t(ADBKey::y)
#define BindDirect(x) Bind(x, x)
BindDirect(BackTick);

2
Machines/Apple/AppleIIgs/ADB.cpp
View File

@ -71,7 +71,7 @@ uint8_t GLU::get_any_key_down() {
uint8_t GLU::get_mouse_data() {
// Alternates between returning x and y values.
//
// b7: 1 = button is up; 0 = button is down.
// b7: 1 = button is up; 0 = button is down.
// b6: delta sign bit; 1 = negative.
// b5–b0: mouse delta.

10
Machines/Apple/AppleIIgs/AppleIIgs.cpp
View File

@ -203,8 +203,8 @@ class ConcreteMachine:
memory_(target.model >= Analyser::Static::AppleIIgs::Target::Model::ROM03),
iwm_(CLOCK_RATE / 2),
drives35_{
{CLOCK_RATE / 2, true},
{CLOCK_RATE / 2, true}
{CLOCK_RATE / 2, true},
{CLOCK_RATE / 2, true}
},
drives525_{
{CLOCK_RATE / 2},
@ -1144,9 +1144,9 @@ class ConcreteMachine:
Apple::Clock::ParallelClock clock_;
JustInTimeActor<Apple::IIgs::Video::Video, Cycles, 1, 2> video_; // i.e. run video at 7Mhz.
JustInTimeActor<Apple::IIgs::ADB::GLU, Cycles, 1, 4> adb_glu_; // i.e. 3,579,545Mhz.
Zilog::SCC::z8530 scc_;
JustInTimeActor<Apple::IWM, Cycles, 1, 2> iwm_;
Cycles cycles_since_clock_tick_;
Zilog::SCC::z8530 scc_;
JustInTimeActor<Apple::IWM, Cycles, 1, 2> iwm_;
Cycles cycles_since_clock_tick_;
Apple::Macintosh::DoubleDensityDrive drives35_[2];
Apple::Disk::DiskIIDrive drives525_[2];

2
Machines/Apple/AppleIIgs/MemoryMap.hpp
View File

@ -642,7 +642,7 @@ class MemoryMap {
// TODO: branching below on region.read/write is predicated on the idea that extra scratch space
// would be less efficient. Verify that?
#define MemoryMapRegion(map, address) map.regions[map.region_map[address >> 8]]
#define MemoryMapRegion(map, address) map.regions[map.region_map[address >> 8]]
#define MemoryMapRead(region, address, value) *value = region.read ? region.read[address] : 0xff
// The below encapsulates the fact that I've yet to determine whether Apple intends to

2
Machines/Apple/AppleIIgs/Video.hpp
View File

@ -114,7 +114,7 @@ class Video: public Apple::II::VideoSwitches<Cycles> {
switch(m) {
case GraphicsMode::Text: return PixelBufferFormat::Text;
case GraphicsMode::DoubleText: return PixelBufferFormat::DoubleText;
default: return PixelBufferFormat::NTSC;
default: return PixelBufferFormat::NTSC;
case GraphicsMode::DoubleHighResMono: return PixelBufferFormat::NTSCMono;
case GraphicsMode::SuperHighRes: return PixelBufferFormat::SuperHighRes;
}

42
Machines/Apple/Macintosh/Macintosh.cpp
View File

@ -88,17 +88,17 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
Inputs::Keyboard::Key::LeftOption, Inputs::Keyboard::Key::RightOption,
Inputs::Keyboard::Key::LeftMeta, Inputs::Keyboard::Key::RightMeta,
}),
mc68000_(*this),
iwm_(CLOCK_RATE),
video_(audio_, drive_speed_accumulator_),
via_(via_port_handler_),
via_port_handler_(*this, clock_, keyboard_, audio_, iwm_, mouse_),
scsi_bus_(CLOCK_RATE * 2),
scsi_(scsi_bus_, CLOCK_RATE * 2),
hard_drive_(scsi_bus_, 6 /* SCSI ID */),
drives_{
{CLOCK_RATE, model >= Analyser::Static::Macintosh::Target::Model::Mac512ke},
{CLOCK_RATE, model >= Analyser::Static::Macintosh::Target::Model::Mac512ke}
mc68000_(*this),
iwm_(CLOCK_RATE),
video_(audio_, drive_speed_accumulator_),
via_(via_port_handler_),
via_port_handler_(*this, clock_, keyboard_, audio_, iwm_, mouse_),
scsi_bus_(CLOCK_RATE * 2),
scsi_(scsi_bus_, CLOCK_RATE * 2),
hard_drive_(scsi_bus_, 6 /* SCSI ID */),
drives_{
{CLOCK_RATE, model >= Analyser::Static::Macintosh::Target::Model::Mac512ke},
{CLOCK_RATE, model >= Analyser::Static::Macintosh::Target::Model::Mac512ke}
},
mouse_(1) {
@ -759,20 +759,20 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
Keyboard keyboard_;
MOS::MOS6522::MOS6522<VIAPortHandler> via_;
VIAPortHandler via_port_handler_;
VIAPortHandler via_port_handler_;
Zilog::SCC::z8530 scc_;
Zilog::SCC::z8530 scc_;
SCSI::Bus scsi_bus_;
NCR::NCR5380::NCR5380 scsi_;
NCR::NCR5380::NCR5380 scsi_;
SCSI::Target::Target<SCSI::DirectAccessDevice> hard_drive_;
bool scsi_bus_is_clocked_ = false;
bool scsi_bus_is_clocked_ = false;
HalfCycles via_clock_;
HalfCycles real_time_clock_;
HalfCycles keyboard_clock_;
HalfCycles time_since_video_update_;
HalfCycles time_until_video_event_;
HalfCycles time_since_mouse_update_;
HalfCycles via_clock_;
HalfCycles real_time_clock_;
HalfCycles keyboard_clock_;
HalfCycles time_since_video_update_;
HalfCycles time_until_video_event_;
HalfCycles time_since_mouse_update_;
bool ROM_is_overlay_ = true;
int phase_ = 1;

4
Machines/Apple/Macintosh/Video.cpp
View File

@ -36,9 +36,9 @@ constexpr uint64_t PixelMask = 0x0102040810204080;
Video::Video(DeferredAudio &audio, DriveSpeedAccumulator &drive_speed_accumulator) :
audio_(audio),
drive_speed_accumulator_(drive_speed_accumulator),
crt_(704, 1, 370, 6, Outputs::Display::InputDataType::Luminance1) {
crt_(704, 1, 370, 6, Outputs::Display::InputDataType::Luminance1) {
crt_.set_display_type(Outputs::Display::DisplayType::RGB);
crt_.set_display_type(Outputs::Display::DisplayType::RGB);
// UGLY HACK. UGLY, UGLY HACK. UGLY!
// The OpenGL scan target fails properly to place visible areas which are not 4:3.

2
Machines/Atari/2600/TIA.cpp
View File

@ -23,7 +23,7 @@ namespace {
}
TIA::TIA():
crt_(cycles_per_line * 2 - 1, 1, Outputs::Display::Type::NTSC60, Outputs::Display::InputDataType::Luminance8Phase8) {
crt_(cycles_per_line * 2 - 1, 1, Outputs::Display::Type::NTSC60, Outputs::Display::InputDataType::Luminance8Phase8) {
set_output_mode(OutputMode::NTSC);

8
Machines/Atari/ST/Video.cpp
View File

@ -173,7 +173,7 @@ void Video::run_for(HalfCycles duration) {
if(horizontal_timings.reset_blank > x_) next_event = std::min(next_event, horizontal_timings.reset_blank);
if(horizontal_timings.set_blank > x_) next_event = std::min(next_event, horizontal_timings.set_blank);
if(horizontal_timings.reset_enable > x_) next_event = std::min(next_event, horizontal_timings.reset_enable);
if(horizontal_timings.set_enable > x_) next_event = std::min(next_event, horizontal_timings.set_enable);
if(horizontal_timings.set_enable > x_) next_event = std::min(next_event, horizontal_timings.set_enable);
// Check for events that are relative to existing latched state.
if(line_length_.hsync_start > x_) next_event = std::min(next_event, line_length_.hsync_start);
@ -301,7 +301,7 @@ void Video::run_for(HalfCycles duration) {
if(horizontal_timings.reset_blank == x_) horizontal_.blank = false;
else if(horizontal_timings.set_blank == x_) horizontal_.blank = true;
else if(horizontal_timings.reset_enable == x_) horizontal_.enable = false;
else if(horizontal_timings.set_enable == x_) horizontal_.enable = true;
else if(horizontal_timings.set_enable == x_) horizontal_.enable = true;
else if(line_length_.hsync_start == x_) { horizontal_.sync = true; horizontal_.enable = false; }
else if(line_length_.hsync_end == x_) horizontal_.sync = false;
@ -746,7 +746,7 @@ void Video::VideoStream::output_pixels(int duration) {
if(pixels) {
int leftover_duration = pixels;
switch(bpp_) {
default: leftover_duration >>= 1; break;
default: leftover_duration >>= 1; break;
case OutputBpp::Two: break;
case OutputBpp::Four: leftover_duration <<= 1; break;
}
@ -759,7 +759,7 @@ void Video::VideoStream::flush_pixels() {
// Flush only if there's something to flush.
if(pixel_pointer_) {
switch(bpp_) {
case OutputBpp::One: crt_.output_data(pixel_pointer_); break;
case OutputBpp::One: crt_.output_data(pixel_pointer_); break;
default: crt_.output_data(pixel_pointer_ << 1, size_t(pixel_pointer_)); break;
case OutputBpp::Four: crt_.output_data(pixel_pointer_ << 2, size_t(pixel_pointer_)); break;
}

2
Machines/Enterprise/Keyboard.hpp
View File

@ -18,7 +18,7 @@ namespace Enterprise {
enum class Key: uint16_t {
N = 0x0000 | 0x01, Backslash = 0x0000 | 0x02, B = 0x0000 | 0x04, C = 0x0000 | 0x08,
V = 0x0000 | 0x10, X = 0x0000 | 0x20, Z = 0x0000 | 0x40, LeftShift = 0x0000 | 0x80,
V = 0x0000 | 0x10, X = 0x0000 | 0x20, Z = 0x0000 | 0x40, LeftShift = 0x0000 | 0x80,
H = 0x0100 | 0x01, Lock = 0x0100 | 0x02, G = 0x0100 | 0x04, D = 0x0100 | 0x08,
F = 0x0100 | 0x10, S = 0x0100 | 0x20, A = 0x0100 | 0x40, Control = 0x0100 | 0x80,

4
Machines/ScanProducer.hpp
View File

@ -82,8 +82,8 @@ class ScanProducer {
switch(get_display_type()) {
default:
case Outputs::Display::DisplayType::RGB: return Configurable::Display::RGB;
case Outputs::Display::DisplayType::SVideo: return Configurable::Display::SVideo;
case Outputs::Display::DisplayType::CompositeColour: return Configurable::Display::CompositeColour;
case Outputs::Display::DisplayType::SVideo: return Configurable::Display::SVideo;
case Outputs::Display::DisplayType::CompositeColour: return Configurable::Display::CompositeColour;
case Outputs::Display::DisplayType::CompositeMonochrome: return Configurable::Display::CompositeMonochrome;
}
}

4
Machines/Sinclair/ZXSpectrum/ZXSpectrum.cpp
View File

@ -119,7 +119,7 @@ using CharacterMapper = Sinclair::ZX::Keyboard::CharacterMapper;
template<Model model> class ConcreteMachine:
public Activity::Source,
public ClockingHint::Observer,
public ClockingHint::Observer,
public Configurable::Device,
public CPU::Z80::BusHandler,
public Machine,
@ -153,7 +153,7 @@ template<Model model> class ConcreteMachine:
case Model::OneTwoEightK: rom_name = ROM::Name::Spectrum128k; break;
case Model::Plus2: rom_name = ROM::Name::SpecrumPlus2; break;
case Model::Plus2a:
case Model::Plus3: rom_name = ROM::Name::SpectrumPlus3; break;
case Model::Plus3: rom_name = ROM::Name::SpectrumPlus3; break;
// TODO: possibly accept the +3 ROM in multiple parts?
}
const auto request = ROM::Request(rom_name);

10
Machines/Utility/ROMCatalogue.cpp
View File

@ -523,16 +523,16 @@ Description::Description(Name name) {
case Name::Spectrum48k: *this = Description(name, "ZXSpectrum", "the 48kb ROM", "48.rom", 16 * 1024, 0xddee531fu); break;
case Name::Spectrum128k: *this = Description(name, "ZXSpectrum", "the 128kb ROM", "128.rom", 32 * 1024, 0x2cbe8995u); break;
case Name::SpecrumPlus2: *this = Description(name, "ZXSpectrum", "the +2 ROM", "plus2.rom", 32 * 1024, 0xe7a517dcu); break;
case Name::SpecrumPlus2: *this = Description(name, "ZXSpectrum", "the +2 ROM", "plus2.rom", 32 * 1024, 0xe7a517dcu); break;
case Name::SpectrumPlus3: {
const std::initializer_list<uint32_t> crcs = { 0x96e3c17a, 0xbe0d9ec4 };
*this = Description(name, "ZXSpectrum", "the +2a/+3 ROM", "plus3.rom", 64 * 1024, crcs);
} break;
case Name::AcornBASICII: *this = Description(name, "Electron", "the Acorn BASIC II ROM", "basic.rom", 16*1024, 0x79434781u); break;
case Name::PRESADFSSlot1: *this = Description(name, "Electron", "the E00 ADFS ROM, first slot", "ADFS-E00_1.rom", 16*1024, 0x51523993u); break;
case Name::AcornBASICII: *this = Description(name, "Electron", "the Acorn BASIC II ROM", "basic.rom", 16*1024, 0x79434781u); break;
case Name::PRESADFSSlot1: *this = Description(name, "Electron", "the E00 ADFS ROM, first slot", "ADFS-E00_1.rom", 16*1024, 0x51523993u); break;
case Name::PRESADFSSlot2: *this = Description(name, "Electron", "the E00 ADFS ROM, second slot", "ADFS-E00_2.rom", 16*1024, 0x8d17de0eu); break;
case Name::AcornADFS: *this = Description(name, "Electron", "the Acorn ADFS ROM", "adfs.rom", 16*1024, 0x3289bdc6u); break;
case Name::AcornADFS: *this = Description(name, "Electron", "the Acorn ADFS ROM", "adfs.rom", 16*1024, 0x3289bdc6u); break;
case Name::Acorn1770DFS: *this = Description(name, "Electron", "the 1770 DFS ROM", "DFS-1770-2.20.rom", 16*1024, 0xf3dc9bc5u); break;
case Name::PRESAdvancedPlus6:
*this = Description(name, "Electron", "the 8kb Advanced Plus 6 ROM", "AP6v133.rom", 8*1024, 0xe0013cfcu);
@ -542,7 +542,7 @@ Description::Description(Name name) {
break;
case Name::MasterSystemJapaneseBIOS: *this = Description(name, "MasterSystem", "the Japanese Master System BIOS", "japanese-bios.sms", 8*1024, 0x48d44a13u); break;
case Name::MasterSystemWesternBIOS: *this = Description(name, "MasterSystem", "the European/US Master System BIOS", "bios.sms", 8*1024, 0x0072ed54u); break;
case Name::MasterSystemWesternBIOS: *this = Description(name, "MasterSystem", "the European/US Master System BIOS", "bios.sms", 8*1024, 0x0072ed54u); break;
case Name::Commodore1540: *this = Description(name, "Commodore1540", "the 1540 ROM", "1540.bin", 16*1024, 0x718d42b1u); break;
case Name::Commodore1541: *this = Description(name, "Commodore1540", "the 1541 ROM", "1541.bin", 16*1024, 0xfb760019); break;

8
OSBindings/Mac/Clock Signal/ScanTarget/CSScanTarget.mm
View File

@ -693,9 +693,9 @@ using BufferingScanTarget = Outputs::Display::BufferingScanTarget;
};
const FragmentSamplerDictionary samplerDictionary[8] = {
// Composite formats.
{@"compositeSampleLuminance1", nil, @"sampleLuminance1", @"sampleLuminance1", @"sampleLuminance1", @"sampleLuminance1"},
{@"compositeSampleLuminance8", nil, @"sampleLuminance8", @"sampleLuminance8WithGamma", @"sampleLuminance8", @"sampleLuminance8WithGamma"},
{@"compositeSamplePhaseLinkedLuminance8", nil, @"samplePhaseLinkedLuminance8", @"samplePhaseLinkedLuminance8WithGamma", @"samplePhaseLinkedLuminance8", @"samplePhaseLinkedLuminance8WithGamma"},
{@"compositeSampleLuminance1", nil, @"sampleLuminance1", @"sampleLuminance1", @"sampleLuminance1", @"sampleLuminance1"},
{@"compositeSampleLuminance8", nil, @"sampleLuminance8", @"sampleLuminance8WithGamma", @"sampleLuminance8", @"sampleLuminance8WithGamma"},
{@"compositeSamplePhaseLinkedLuminance8", nil, @"samplePhaseLinkedLuminance8", @"samplePhaseLinkedLuminance8WithGamma", @"samplePhaseLinkedLuminance8", @"samplePhaseLinkedLuminance8WithGamma"},
// S-Video formats.
{@"compositeSampleLuminance8Phase8", @"sampleLuminance8Phase8", @"directCompositeSampleLuminance8Phase8", @"directCompositeSampleLuminance8Phase8WithGamma", @"directCompositeSampleLuminance8Phase8", @"directCompositeSampleLuminance8Phase8WithGamma"},
@ -808,7 +808,7 @@ using BufferingScanTarget = Outputs::Display::BufferingScanTarget;
if(_pipeline != Pipeline::DirectToDisplay) {
// Create the composition render pass.
pipelineDescriptor.colorAttachments[0].pixelFormat = _compositionTexture.pixelFormat;
pipelineDescriptor.colorAttachments[0].pixelFormat = _compositionTexture.pixelFormat;
pipelineDescriptor.vertexFunction = [library newFunctionWithName:@"scanToComposition"];
pipelineDescriptor.fragmentFunction =
[library newFunctionWithName:isSVideoOutput ? samplerDictionary[int(modals.input_data_type)].compositionSVideo : samplerDictionary[int(modals.input_data_type)].compositionComposite];

4
OSBindings/Mac/Clock Signal/ScanTarget/ScanTarget.metal
View File

@ -380,12 +380,12 @@ half3 convertRed1Green1Blue1(SourceInterpolator vert, texture2d<ushort> texture)
} \
\
fragment half4 directCompositeSample##name(SourceInterpolator vert [[stage_in]], texture2d<pixelType> texture [[texture(0)]], constant Uniforms &uniforms [[buffer(0)]]) { \
const half level = composite##name(vert, texture, uniforms, quadrature(vert.colourPhase)); \
const half level = composite##name(vert, texture, uniforms, quadrature(vert.colourPhase)); \
return half4(half3(level), uniforms.outputAlpha); \
} \
\
fragment half4 directCompositeSample##name##WithGamma(SourceInterpolator vert [[stage_in]], texture2d<pixelType> texture [[texture(0)]], constant Uniforms &uniforms [[buffer(0)]]) { \
const half level = pow(composite##name(vert, texture, uniforms, quadrature(vert.colourPhase)), uniforms.outputGamma); \
const half level = pow(composite##name(vert, texture, uniforms, quadrature(vert.colourPhase)), uniforms.outputGamma); \
return half4(half3(level), uniforms.outputAlpha); \
}

2
OSBindings/Mac/Clock SignalTests/6522Tests.swift
View File

@ -200,7 +200,7 @@ class MOS6522Tests: XCTestCase {
// Conclusions:
//
// after inital ACR and port B value: [original data if not in PB7 output mode, otherwise 1]
// after starting timer 1: [original data if not in PB7 output mode, otherwise 0]
// after starting timer 1: [original data if not in PB7 output mode, otherwise 0]
// after final ACR value: [original data if not in PB7 output mode, 1 if has transitioned to PB7 mode, 0 if was already in PB7 mode]
// after timer 1 expiry: [original data if not in PB7 mode, 1 if timer has expired while in PB7 mode]
//

2
OSBindings/Mac/Clock SignalTests/WolfgangLorenzTests.swift
View File

@ -375,7 +375,7 @@ class WolfgangLorenzTests: XCTestCase, CSTestMachineTrapHandler {
let bundle = Bundle(for: type(of: self))
let mainBundle = Bundle.main
if let testFilename = bundle.url(forResource: name, withExtension: nil),
if let testFilename = bundle.url(forResource: name, withExtension: nil),
let kernelFilename = mainBundle.url(forResource: "kernal.901227-02", withExtension: "bin", subdirectory: "ROMImages/Commodore64") {
if let testData = try? Data(contentsOf: testFilename), let kernelData = try? Data(contentsOf: kernelFilename) {

2
OSBindings/Mac/Clock SignalTests/Z80MemptrTests.swift
View File

@ -141,7 +141,7 @@ class Z80MemptrTester: XCTestCase {
0xb1, // CPIR
0xb2, // INIR
0xb3, // OUIR
0xb8, // LDDR
0xb8, // LDDR
0xb9, // CPDR
0xba, // INDR
0xbb, // OTDR

4
OSBindings/Mac/Clock SignalTests/x86DecoderTests.mm
View File

@ -180,8 +180,8 @@ decode(const std::initializer_list<uint8_t> &stream, bool set_32_bit = false) {
test(instructions[11], DataSize::Word, Operation::XCHG, Source::eAX, Source::eSP);
// ODA has:
// c4 (bad)
// d4 93 aam $0x93
// c4 (bad)
// d4 93 aam $0x93
//
// That assumes that upon discovering that the d4 doesn't make a valid LES,
// it can become an instruction byte. I'm not persuaded. So I'm taking:

12
Processors/6502/Implementation/6502Implementation.hpp
View File

@ -421,12 +421,12 @@ template <Personality personality, typename T, bool uses_ready_line> void Proces
case OperationINC: operand_++; flags_.set_nz(operand_); continue;
case OperationDEC: operand_--; flags_.set_nz(operand_); continue;
case OperationINA: a_++; flags_.set_nz(a_); continue;
case OperationDEA: a_--; flags_.set_nz(a_); continue;
case OperationINX: x_++; flags_.set_nz(x_); continue;
case OperationDEX: x_--; flags_.set_nz(x_); continue;
case OperationINY: y_++; flags_.set_nz(y_); continue;
case OperationDEY: y_--; flags_.set_nz(y_); continue;
case OperationINA: a_++; flags_.set_nz(a_); continue;
case OperationDEA: a_--; flags_.set_nz(a_); continue;
case OperationINX: x_++; flags_.set_nz(x_); continue;
case OperationDEX: x_--; flags_.set_nz(x_); continue;
case OperationINY: y_++; flags_.set_nz(y_); continue;
case OperationDEY: y_--; flags_.set_nz(y_); continue;
case OperationANE:
a_ = (a_ | 0xee) & operand_ & x_;

2
Processors/65816/Implementation/65816Implementation.hpp
View File

@ -504,7 +504,7 @@ template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler,
// Performance.
//
#define LDA(src) registers_.a.full = (registers_.a.full & registers_.m_masks[0]) | (src & registers_.m_masks[1])
#define LDA(src) registers_.a.full = (registers_.a.full & registers_.m_masks[0]) | (src & registers_.m_masks[1])
#define LDXY(dest, src) dest = (src) & registers_.x_mask
case OperationPerform:

4
Processors/65816/Implementation/65816Storage.hpp
View File

@ -80,8 +80,8 @@ enum MicroOp: uint8_t {
OperationConstructAbsoluteLongX,
/// Calculates an a, x address; if:
/// there was no carry into the top byte of the address; and
/// the process or in emulation or 8-bit index mode;
/// there was no carry into the top byte of the address; and
/// the process or in emulation or 8-bit index mode;
/// then it also skips the next micro-op.
OperationConstructAbsoluteXRead,

10
Processors/68000/68000.hpp
View File

@ -53,7 +53,7 @@ struct Microcycle {
static constexpr OperationT SelectWord = 1 << 1;
/// If set, indicates a read. Otherwise, a write.
static constexpr OperationT Read = 1 << 2;
static constexpr OperationT Read = 1 << 2;
// Two-bit gap deliberately left here for PermitRead/Write below.
@ -69,10 +69,10 @@ struct Microcycle {
static constexpr OperationT Reset = 1 << 7;
/// Contains the value of line FC0 if it is not implicit via InterruptAcknowledge.
static constexpr OperationT IsData = 1 << 8;
static constexpr OperationT IsData = 1 << 8;
/// Contains the value of line FC1 if it is not implicit via InterruptAcknowledge.
static constexpr OperationT IsProgram = 1 << 9;
static constexpr OperationT IsProgram = 1 << 9;
/// The interrupt acknowledge cycle is that during which the 68000 seeks to obtain the vector for
/// an interrupt it plans to observe. Noted on a real 68000 by all FCs being set to 1.
@ -80,7 +80,7 @@ struct Microcycle {
/// Represents the state of the 68000's valid memory address line — indicating whether this microcycle
/// is synchronised with the E clock to satisfy a valid peripheral address request.
static constexpr OperationT IsPeripheral = 1 << 11;
static constexpr OperationT IsPeripheral = 1 << 11;
/// Provides the 68000's bus grant line — indicating whether a bus request has been acknowledged.
static constexpr OperationT BusGrant = 1 << 12;
@ -292,7 +292,7 @@ struct Microcycle {
// PermitRead and PermitWrite are used as part of the read/write mask
// supplied to @c apply; they are picked to be small enough values that
// a byte can be used for storage.
static constexpr OperationT PermitRead = 1 << 3;
static constexpr OperationT PermitRead = 1 << 3;
static constexpr OperationT PermitWrite = 1 << 4;
/*!

26
Processors/68000/Implementation/68000Implementation.hpp
View File

@ -482,7 +482,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
// So the below is a cross-your-fingers guess based on the constraints
// that the information writen, from lowest address to highest is:
//
// R/W, I/N, function code word; [at -14]
// R/W, I/N, function code word; [at -14]
// access address; [-12]
// instruction register; [-8]
// status register; [-6]
@ -716,9 +716,9 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
static_assert( \
InstructionSet::M68k::operand_flags<InstructionSet::M68k::Model::M68000, InstructionSet::M68k::Operation::x>() == \
InstructionSet::M68k::operand_flags<InstructionSet::M68k::Model::M68000, InstructionSet::M68k::Operation::y>() && \
InstructionSet::M68k::operand_size<InstructionSet::M68k::Operation::x>() == \
InstructionSet::M68k::operand_size<InstructionSet::M68k::Operation::x>() == \
InstructionSet::M68k::operand_size<InstructionSet::M68k::Operation::y>() && \
InstructionSet::M68k::requires_supervisor<InstructionSet::M68k::Model::M68000>(InstructionSet::M68k::Operation::x) == \
InstructionSet::M68k::requires_supervisor<InstructionSet::M68k::Model::M68000>(InstructionSet::M68k::Operation::x) == \
InstructionSet::M68k::requires_supervisor<InstructionSet::M68k::Model::M68000>(InstructionSet::M68k::Operation::y) \
); \
[[fallthrough]];
@ -751,10 +751,10 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
})
Duplicate(CLRb, NEGXb) Duplicate(NEGb, NEGXb) Duplicate(NOTb, NEGXb)
StdCASE(NEGXb, perform_state_ = Perform_np);
StdCASE(NEGXb, perform_state_ = Perform_np);
Duplicate(CLRw, NEGXw) Duplicate(NEGw, NEGXw) Duplicate(NOTw, NEGXw)
StdCASE(NEGXw, perform_state_ = Perform_np);
StdCASE(NEGXw, perform_state_ = Perform_np);
Duplicate(CLRl, NEGXl) Duplicate(NEGl, NEGXl) Duplicate(NOTl, NEGXl)
StdCASE(NEGXl,
@ -765,11 +765,11 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
}
);
StdCASE(SWAP, perform_state_ = Perform_np);
StdCASE(EXG, perform_state_ = Perform_np_n);
StdCASE(SWAP, perform_state_ = Perform_np);
StdCASE(EXG, perform_state_ = Perform_np_n);
StdCASE(EXTbtow, perform_state_ = Perform_np);
StdCASE(EXTwtol, perform_state_ = Perform_np);
StdCASE(EXTbtow, perform_state_ = Perform_np);
StdCASE(EXTwtol, perform_state_ = Perform_np);
StdCASE(MOVEb, perform_state_ = MOVE_b);
Duplicate(MOVEAw, MOVEw)
@ -987,10 +987,10 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
});
Duplicate(ORItoCCR, EORItoCCR); Duplicate(ANDItoCCR, EORItoCCR);
StdCASE(EORItoCCR, perform_state_ = LogicalToSR);
StdCASE(EORItoCCR, perform_state_ = LogicalToSR);
Duplicate(ORItoSR, EORItoSR); Duplicate(ANDItoSR, EORItoSR);
StdCASE(EORItoSR, perform_state_ = LogicalToSR);
StdCASE(EORItoSR, perform_state_ = LogicalToSR);
StdCASE(MOVEMtoRl, perform_state_ = MOVEMtoR);
StdCASE(MOVEMtoRw, perform_state_ = MOVEMtoR);
@ -1032,8 +1032,8 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
}
});
StdCASE(MOVEtoCCR, perform_state_ = MOVEtoCCRSR);
StdCASE(MOVEtoSR, perform_state_ = MOVEtoCCRSR);
StdCASE(MOVEtoCCR, perform_state_ = MOVEtoCCRSR);
StdCASE(MOVEtoSR, perform_state_ = MOVEtoCCRSR);
StdCASE(MOVEfromSR, {
if(instruction_.mode(0) == Mode::DataRegisterDirect) {
perform_state_ = Perform_np_n;

2
Storage/MassStorage/Formats/HFV.cpp
View File

@ -51,7 +51,7 @@ void HFV::set_block(size_t address, const std::vector<uint8_t> &contents) {
file_.write(contents);
} else {
writes_[address] = contents;
}
}
}
void HFV::set_drive_type(Encodings::Macintosh::DriveType drive_type) {

4
Storage/MassStorage/SCSI/SCSI.hpp
View File

@ -34,9 +34,9 @@ constexpr BusState DefaultBusState = 0;
*/
enum Line: BusState {
/// Provides the value currently on the data lines.
Data = 0xff,
Data = 0xff,
/// Parity of the data lines.
Parity = 1 << 8,
Parity = 1 << 8,
/// Set if the SEL line is currently selecting a target.
/// Reset if it is selecting an initiator.
SelectTarget = 1 << 9,

2
Storage/MassStorage/SCSI/TargetImplementation.hpp
View File

@ -139,7 +139,7 @@ template <typename Executor> void Target<Executor>::scsi_bus_did_change(Bus *, B
bus_state_ &= ~0xff;
switch(phase_) {
case Phase::SendingData: bus_state_ |= data_[data_pointer_]; break;
case Phase::SendingData: bus_state_ |= data_[data_pointer_]; break;
case Phase::SendingStatus: bus_state_ |= BusState(status_); break;
default:
case Phase::SendingMessage: bus_state_ |= BusState(message_); break;

2
Storage/State/Z80.cpp
View File

@ -96,7 +96,7 @@ std::unique_ptr<Analyser::Static::Target> Z80::load(const std::string &file_name
// Ignored from the next byte:
//
// bit 2 = 1 => issue 2 emulation
// bit 2 = 1 => issue 2 emulation
// bit 3 = 1 => double interrupt frequency (?)
// bit 4–5 => video synchronisation (to do with emulation hackery?)
// bit 6–7 => joystick type