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https://github.com/TomHarte/CLK.git
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Adds absolute, x; absolute,y; and accumulator addressing modes.
Now covered: 80/256 opcodes, from 2/6 pages of the data sheet; or 16/47 bus programs.
This commit is contained in:
Thomas Harte
parent
8c11df52bf
commit
2957a31f40
@ -28,8 +28,12 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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case LDA: case LDX: case LDY:
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// The access type for these is arbitrary, though consistency is beneficial.
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// The access type for the rest of these ::Reads is arbitrary.
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case JMP: case JSR: case JML: case JSL:
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case ASL: case DEC: case INC: case LSR:
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case ROL: case ROR: case TRB: case TSB:
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return AccessType::Read;
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case STA: case STX: case STY: case STZ:
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@ -133,6 +137,19 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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}
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}
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static void read_modify_write(bool is8bit, const std::function<void(MicroOp)> &target) {
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if(!is8bit) target(CycleFetchIncrementData); // Data low.
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target(CycleFetchData); // Data [high].
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if(!is8bit) target(CycleFetchData); // 16-bit: reread final byte of data.
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else target(CycleStoreData); // 8-bit rewrite final byte of data.
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target(OperationPerform); // Perform operation within the data buffer.
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if(!is8bit) target(CycleStoreDecrementData); // Data high.
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target(CycleStoreData); // Data [low].
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}
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// 1a. Absolute; a.
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static void absolute(AccessType type, bool is8bit, const std::function<void(MicroOp)> &target) {
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target(CycleFetchIncrementPC); // AAL.
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@ -167,16 +184,7 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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target(CycleFetchIncrementPC); // AAH.
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target(OperationConstructAbsolute); // Calculate data address.
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if(!is8bit) target(CycleFetchIncrementData); // Data low.
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target(CycleFetchData); // Data [high].
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if(!is8bit) target(CycleFetchData); // 16-bit: reread final byte of data.
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else target(CycleStoreData); // 8-bit rewrite final byte of data.
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target(OperationPerform); // Perform operation within the data buffer.
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if(!is8bit) target(CycleStoreDecrementData); // Data high.
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target(CycleStoreData); // Data [low].
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read_modify_write(is8bit, target);
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};
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// 2a. Absolute Indexed Indirect; (a, x), JMP.
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@ -281,6 +289,60 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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read_write(type, is8bit, target);
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}
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// 6a. Absolute, X; a, x.
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static void absolute_x(AccessType type, bool is8bit, const std::function<void(MicroOp)> &target) {
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target(CycleFetchIncrementPC); // AAL.
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target(CycleFetchIncrementPC); // AAH.
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if(type == AccessType::Read) {
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target(OperationConstructAbsoluteXRead); // Calculate data address, potentially skipping the next fetch.
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} else {
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target(OperationConstructAbsoluteX); // Calculate data address.
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}
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target(CycleFetchIncorrectDataAddress); // Do the dummy read if necessary; OperationConstructAbsoluteX
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// will skip this if it isn't required.
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read_write(type, is8bit, target);
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}
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// 6b. Absolute, X; a, x, read-modify-write.
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static void absolute_x_rmw(AccessType, bool is8bit, const std::function<void(MicroOp)> &target) {
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target(CycleFetchIncrementPC); // AAL.
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target(CycleFetchIncrementPC); // AAH.
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target(OperationConstructAbsoluteX); // Calculate data address.
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target(CycleFetchIncorrectDataAddress); // Perform dummy read.
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read_modify_write(is8bit, target);
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}
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// 6a. Absolute, Y; a, y.
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static void absolute_y(AccessType type, bool is8bit, const std::function<void(MicroOp)> &target) {
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target(CycleFetchIncrementPC); // AAL.
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target(CycleFetchIncrementPC); // AAH.
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if(type == AccessType::Read) {
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target(OperationConstructAbsoluteYRead); // Calculate data address, potentially skipping the next fetch.
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} else {
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target(OperationConstructAbsoluteY); // Calculate data address.
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}
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target(CycleFetchIncorrectDataAddress); // Do the dummy read if necessary; OperationConstructAbsoluteX
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// will skip this if it isn't required.
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read_write(type, is8bit, target);
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}
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// 7. Accumulator; A.
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static void accumulator(AccessType, bool, const std::function<void(MicroOp)> &target) {
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target(CycleFetchPC); // IO.
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// TODO: seriously consider a-specific versions of all relevant operations;
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// the cost of interpreting three things here is kind of silly.
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target(OperationCopyAToData);
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target(OperationPerform);
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target(OperationCopyDataToA);
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}
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};
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// TEMPORARY. Kneejerk way to get a step debug of 65816 storage construction.
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@ -302,11 +364,11 @@ ProcessorStorage::ProcessorStorage() {
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/* 0x07 ORA [d] */
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/* 0x08 PHP s */
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/* 0x09 ORA # */
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/* 0x0a ASL a */
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/* 0x0a ASL A */ op(accumulator, ASL);
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/* 0x0b PHD s */
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/* 0x0c TSB a */
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/* 0x0c TSB a */ op(absolute_rmw, TSB);
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/* 0x0d ORA a */ op(absolute, ORA);
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/* 0x0e ASL a */
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/* 0x0e ASL a */ op(absolute_rmw, ASL);
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/* 0x0f ORA al */ op(absolute_long, ORA);
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/* 0x10 BPL r */
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@ -318,12 +380,12 @@ ProcessorStorage::ProcessorStorage() {
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/* 0x16 ASL d, x */
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/* 0x17 ORA [d], y */
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/* 0x18 CLC i */
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/* 0x19 ORA a, y */
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/* 0x1a INC A */
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/* 0x19 ORA a, y */ op(absolute_y, ORA);
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/* 0x1a INC A */ op(accumulator, INC);
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/* 0x1b TCS i */
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/* 0x1c TRB a */
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/* 0x1d ORA a, x */
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/* 0x1e ASL a, x */
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/* 0x1c TRB a */ op(absolute_rmw, TRB);
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/* 0x1d ORA a, x */ op(absolute_x, ORA);
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/* 0x1e ASL a, x */ op(absolute_x_rmw, ASL);
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/* 0x1f ORA al, x */ op(absolute_long_x, ORA);
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/* 0x20 JSR a */ op(absolute_jsr, JSR);
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@ -332,15 +394,15 @@ ProcessorStorage::ProcessorStorage() {
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/* 0x23 JSL al */ op(absolute_long_jsl, JSL);
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/* 0x24 BIT d */
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/* 0x25 AND d */
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/* 0x26 ROL d */
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/* 0x26 ROL d */ op(absolute_x_rmw, ROL);
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/* 0x27 AND [d] */
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/* 0x28 PLP s */
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/* 0x29 AND # */
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/* 0x2a ROL A */
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/* 0x2a ROL A */ op(accumulator, ROL);
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/* 0x2b PLD s */
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/* 0x2c BIT a */ op(absolute, BIT);
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/* 0x2d AND a */ op(absolute, AND);
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/* 0x2e ROL a */
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/* 0x2e ROL a */ op(absolute_rmw, ROL);
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/* 0x2f AND al */ op(absolute_long, AND);
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/* 0x30 BMI R */
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@ -352,11 +414,11 @@ ProcessorStorage::ProcessorStorage() {
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/* 0x36 TOL d, x */
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/* 0x37 AND [d], y */
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/* 0x38 SEC i */
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/* 0x39 AND a, y */
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/* 0x3a DEC A */
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/* 0x39 AND a, y */ op(absolute_y, AND);
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/* 0x3a DEC A */ op(accumulator, DEC);
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/* 0x3b TSC i */
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/* 0x3c BIT a, x */
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/* 0x3d AND a, x */
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/* 0x3c BIT a, x */ op(absolute_x, BIT);
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/* 0x3d AND a, x */ op(absolute_x, AND);
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/* 0x3e TLD a, x */
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/* 0x3f AND al, x */ op(absolute_long_x, AND);
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@ -370,11 +432,11 @@ ProcessorStorage::ProcessorStorage() {
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/* 0x47 EOR [d] */
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/* 0x48 PHA s */
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/* 0x49 EOR # */
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/* 0x4a LSR A */
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/* 0x4a LSR A */ op(accumulator, LSR);
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/* 0x4b PHK s */
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/* 0x4c JMP a */ op(absolute, JMP);
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/* 0x4d EOR a */ op(absolute, EOR);
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/* 0x4e LSR a */
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/* 0x4e LSR a */ op(absolute_rmw, LSR);
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/* 0x4f EOR al */ op(absolute_long, EOR);
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/* 0x50 BVC r */
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@ -386,12 +448,12 @@ ProcessorStorage::ProcessorStorage() {
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/* 0x56 LSR d, x */
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/* 0x57 EOR [d],y */
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/* 0x58 CLI i */
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/* 0x59 EOR a, y */
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/* 0x59 EOR a, y */ op(absolute_y, EOR);
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/* 0x5a PHY s */
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/* 0x5b TCD i */
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/* 0x5c JMP al */ op(absolute_long_jmp, JML); // [sic]; this updates PBR so it's JML.
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/* 0x5d EOR a, x */
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/* 0x5e LSR a, x */
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/* 0x5d EOR a, x */ op(absolute_x, EOR);
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/* 0x5e LSR a, x */ op(absolute_x_rmw, LSR);
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/* 0x5f EOR al, x */ op(absolute_long_x, EOR);
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/* 0x60 RTS s */
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@ -404,11 +466,11 @@ ProcessorStorage::ProcessorStorage() {
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/* 0x67 ADC [d] */
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/* 0x68 PLA s */
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/* 0x69 ADC # */
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/* 0x6a ROR A */
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/* 0x6a ROR A */ op(accumulator, ROR);
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/* 0x6b RTL s */
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/* 0x6c JMP (a) */ op(absolute_indirect_jmp, JMP);
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/* 0x6d ADC a */ op(absolute, ADC);
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/* 0x6e ROR a */
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/* 0x6e ROR a */ op(absolute_rmw, ROR);
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/* 0x6f ADC al */ op(absolute_long, ADC);
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/* 0x70 BVS r */
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@ -420,12 +482,12 @@ ProcessorStorage::ProcessorStorage() {
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/* 0x76 ROR d, x */
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/* 0x77 ADC [d], y */
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/* 0x78 SEI i */
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/* 0x79 ADC a, y */
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/* 0x79 ADC a, y */ op(absolute_y, ADC);
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/* 0x7a PLY s */
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/* 0x7b TDC i */
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/* 0x7c JMP (a, x) */ op(absolute_indexed_indirect_jmp, JMP);
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/* 0x7d ADC a, x */
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/* 0x7e ROR a, x */
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/* 0x7d ADC a, x */ op(absolute_x, ADC);
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/* 0x7e ROR a, x */ op(absolute_x_rmw, ROR);
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/* 0x7f ADC al, x */ op(absolute_long_x, ADC);
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/* 0x80 BRA r */
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@ -454,12 +516,12 @@ ProcessorStorage::ProcessorStorage() {
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/* 0x96 STX d, y */
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/* 0x97 STA [d], y */
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/* 0x98 TYA i */
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/* 0x99 STA a, y */
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/* 0x99 STA a, y */ op(absolute_y, STA);
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/* 0x9a TXS i */
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/* 0x9b TXY i */
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/* 0x9c STZ a */ op(absolute, STZ);
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/* 0x9d STA a, x */
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/* 0x9e STZ a, x */
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/* 0x9d STA a, x */ op(absolute_x, STA);
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/* 0x9e STZ a, x */ op(absolute_x, STZ);
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/* 0x9f STA al, x */ op(absolute_long_x, STA);
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/* 0xa0 LDY # */
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@ -488,12 +550,12 @@ ProcessorStorage::ProcessorStorage() {
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/* 0xb6 LDX d, y */
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/* 0xb7 LDA [d], y */
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/* 0xb8 CLV i */
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/* 0xb9 LDA a, y */
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/* 0xb9 LDA a, y */ op(absolute_y, LDA);
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/* 0xba TSX i */
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/* 0xbb TYX i */
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/* 0xbc LDY a, x */
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/* 0xbd LDA a, x */
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/* 0xbe LDX a, y */
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/* 0xbc LDY a, x */ op(absolute_x, LDY);
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/* 0xbd LDA a, x */ op(absolute_x, LDA);
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/* 0xbe LDX a, y */ op(absolute_y, LDX);
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/* 0xbf LDA al, x */ op(absolute_long_x, LDA);
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/* 0xc0 CPY # */
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@ -510,7 +572,7 @@ ProcessorStorage::ProcessorStorage() {
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/* 0xcb WAI i */
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/* 0xcc CPY a */ op(absolute, CPY);
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/* 0xcd CMP a */ op(absolute, CMP);
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/* 0xce DEC a */
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/* 0xce DEC a */ op(absolute_rmw, DEC);
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/* 0xcf CMP al */ op(absolute_long, CMP);
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/* 0xd0 BNE r */
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@ -522,12 +584,12 @@ ProcessorStorage::ProcessorStorage() {
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/* 0xd6 DEC d, x */
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/* 0xd7 CMP [d], y */
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/* 0xd8 CLD i */
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/* 0xd9 CMP a, y */
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/* 0xd9 CMP a, y */ op(absolute_y, CMP);
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/* 0xda PHX s */
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/* 0xdb STP i */
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/* 0xdc JML (a) */ op(absolute_indirect_jml, JML);
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/* 0xdd CMP a, x */
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/* 0xde DEC a, x */
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/* 0xdd CMP a, x */ op(absolute_x, CMP);
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/* 0xde DEC a, x */ op(absolute_x_rmw, DEC);
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/* 0xdf CMP al, x */ op(absolute_long_x, CMP);
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/* 0xe0 CPX # */
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@ -544,7 +606,7 @@ ProcessorStorage::ProcessorStorage() {
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/* 0xeb XBA i */
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/* 0xec CPX a */ op(absolute, CPX);
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/* 0xed SBC a */ op(absolute, SBC);
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/* 0xee INC a */
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/* 0xee INC a */ op(absolute_rmw, INC);
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/* 0xef SBC al */ op(absolute_long, SBC);
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/* 0xf0 BEQ r */
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@ -556,12 +618,12 @@ ProcessorStorage::ProcessorStorage() {
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/* 0xf6 INC d, x */
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/* 0xf7 SBC [d], y */
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/* 0xf8 SED i */
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/* 0xf9 SBC a, y */
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/* 0xf9 SBC a, y */ op(absolute_y, SBC);
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/* 0xfa PLX s */
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/* 0xfb XCE i */
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/* 0xfc JSR (a, x) */ op(absolute_indexed_indirect_jsr, JMP); // [sic]
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/* 0xfd SBC a, x */
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/* 0xfe INC a, x */
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/* 0xfd SBC a, x */ op(absolute_x, SBC);
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/* 0xfe INC a, x */ op(absolute_x_rmw, INC);
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/* 0xff SBC al, x */ op(absolute_long_x, SBC);
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#undef op
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@ -19,6 +19,9 @@ enum MicroOp: uint8_t {
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CycleFetchData,
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/// Fetches a byte from the data address to the data buffer and increments the data address.
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CycleFetchIncrementData,
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/// Fetches from the address formed by the low byte of the data address and the high byte
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/// of the instruction buffer, throwing the result away.
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CycleFetchIncorrectDataAddress,
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/// Stores a byte from the data buffer.
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CycleStoreData,
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@ -39,6 +42,19 @@ enum MicroOp: uint8_t {
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OperationConstructAbsoluteIndexedIndirect,
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OperationConstructAbsoluteLongX,
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/// Calculates an a, x address; if:
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/// there was no carry into the top byte of the address; and
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/// the process or in emulation or 8-bit index mode;
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/// then it also skips the next micro-op.
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OperationConstructAbsoluteXRead,
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/// Calculates an a, x address.
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OperationConstructAbsoluteX,
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// These are analogous to the X versions above.
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OperationConstructAbsoluteY,
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OperationConstructAbsoluteYRead,
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/// Performs whatever operation goes with this program.
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OperationPerform,
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@ -48,6 +64,9 @@ enum MicroOp: uint8_t {
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/// Copies the current PBR to the data buffer.
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OperationCopyPBRToData,
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OperationCopyAToData,
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OperationCopyDataToA,
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/// Complete this set of micr-ops.
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OperationMoveToNextProgram
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};
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@ -65,6 +84,9 @@ enum Operation: uint8_t {
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// they are implicitly AccessType::Write.
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STA, STX, STY, STZ,
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// These modify the value in the data buffer as part of a read-modify-write.
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ASL, DEC, INC, LSR, ROL, ROR, TRB, TSB,
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/// Loads the PC with the operand from the data buffer.
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JMP,
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