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Remove TODO, add exposition.
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@ -1815,16 +1815,11 @@ template <
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MemoryT &memory,
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IOT &io
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) {
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// Dispatch to a function just like this that is specialised on data size.
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// Fetching will occur in that specialised function, per the overlapping
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// meaning of register names.
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// TODO: incorporate and propagate address size.
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auto size = [](DataSize operation_size, AddressSize address_size) constexpr -> int {
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return int(operation_size) + (int(address_size) << 2);
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};
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// Dispatch to a function specialised on data and address size.
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switch(size(instruction.operation_size(), instruction.address_size())) {
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// 16-bit combinations.
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case size(DataSize::Byte, AddressSize::b16):
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@ -1835,6 +1830,10 @@ template <
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return;
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// 32-bit combinations.
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//
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// The if constexprs below ensure that `perform` isn't compiled for incompatible data or address size and
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// model combinations. So if a caller nominates a 16-bit model it can supply registers and memory objects
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// that don't implement 32-bit registers or accesses.
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case size(DataSize::Byte, AddressSize::b32):
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if constexpr (is_32bit(model)) {
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perform<model, DataSize::Byte, AddressSize::b32>(instruction, status, flow_controller, registers, memory, io);
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@ -1863,8 +1862,8 @@ template <
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default: break;
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}
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// This is reachable only if the data and address size combination in use isn't available on the processor
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// model nominated.
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// This is reachable only if the data and address size combination in use isn't available
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// on the processor model nominated.
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assert(false);
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}
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