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mirror of https://github.com/TomHarte/CLK.git synced 2025-01-14 13:33:42 +00:00

Start sketching the PIT.

This commit is contained in:
Thomas Harte 2023-11-19 07:15:30 -05:00
parent a91449555f
commit 2b69081fff

View File

@ -20,6 +20,27 @@
namespace PCCompatible { namespace PCCompatible {
class PIT {
public:
template <int channel> uint8_t read() {
return 0;
}
template <int channel> void write([[maybe_unused]] uint8_t value) {
}
void set_mode([[maybe_unused]] uint8_t value) {
const int channel = (value >> 6) & 3;
if(channel == 3) {
return;
}
}
private:
enum class LatchMode {
};
};
struct Registers { struct Registers {
public: public:
static constexpr bool is_32bit = false; static constexpr bool is_32bit = false;
@ -269,6 +290,8 @@ struct Memory {
class IO { class IO {
public: public:
IO(PIT &pit) : pit_(pit) {}
template <typename IntT> void out([[maybe_unused]] uint16_t port, [[maybe_unused]] IntT value) { template <typename IntT> void out([[maybe_unused]] uint16_t port, [[maybe_unused]] IntT value) {
switch(port) { switch(port) {
default: default:
@ -320,10 +343,10 @@ class IO {
printf("TODO: CGA write of %02x at %04x\n", value, port); printf("TODO: CGA write of %02x at %04x\n", value, port);
break; break;
case 0x0040: case 0x0041: case 0x0042: case 0x0043: case 0x0040: pit_.write<0>(uint8_t(value)); break;
case 0x0044: case 0x0045: case 0x0046: case 0x0047: case 0x0041: pit_.write<1>(uint8_t(value)); break;
printf("TODO: PIT write of %02x at %04x\n", value, port); case 0x0042: pit_.write<2>(uint8_t(value)); break;
break; case 0x0043: pit_.set_mode(uint8_t(value)); break;
} }
} }
template <typename IntT> IntT in([[maybe_unused]] uint16_t port) { template <typename IntT> IntT in([[maybe_unused]] uint16_t port) {
@ -332,10 +355,9 @@ class IO {
printf("Unhandled in: %04x\n", port); printf("Unhandled in: %04x\n", port);
break; break;
case 0x0040: case 0x0041: case 0x0042: case 0x0043: case 0x0040: return pit_.read<0>();
case 0x0044: case 0x0045: case 0x0046: case 0x0047: case 0x0041: return pit_.read<1>();
printf("TODO: PIT read from %04x\n", port); case 0x0042: return pit_.read<2>();
break;
case 0x0060: case 0x0061: case 0x0062: case 0x0063: case 0x0060: case 0x0061: case 0x0062: case 0x0063:
case 0x0064: case 0x0065: case 0x0066: case 0x0067: case 0x0064: case 0x0065: case 0x0066: case 0x0067:
@ -348,7 +370,7 @@ class IO {
} }
private: private:
PIT &pit_;
}; };
class FlowController { class FlowController {
@ -396,8 +418,8 @@ class ConcreteMachine:
public: public:
ConcreteMachine( ConcreteMachine(
[[maybe_unused]] const Analyser::Static::Target &target, [[maybe_unused]] const Analyser::Static::Target &target,
[[maybe_unused]] const ROMMachine::ROMFetcher &rom_fetcher const ROMMachine::ROMFetcher &rom_fetcher
) { ) : context(pit_) {
// This is actually a MIPS count; try 3 million. // This is actually a MIPS count; try 3 million.
set_clock_rate(3'000'000); set_clock_rate(3'000'000);
@ -451,11 +473,14 @@ class ConcreteMachine:
} }
private: private:
PIT pit_;
struct Context { struct Context {
Context() : Context(PIT &pit) :
segments(registers), segments(registers),
memory(registers, segments), memory(registers, segments),
flow_controller(registers, segments) flow_controller(registers, segments),
io(pit)
{ {
reset(); reset();
} }