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Switch comparative trace tests to 68000 Mk2.

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This commit is contained in:
Thomas Harte 2022-05-25 11:32:00 -04:00
parent 463fbb07f9
commit 2c6b9b4c9d
4 changed files with 23 additions and 22 deletions
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1
OSBindings/Mac/Clock SignalTests/68000ArithmeticTests.mm
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@ -225,6 +225,7 @@
});
auto state = self.machine->get_processor_state();
state.registers.status = ConditionCode::AllConditions;
state.registers.address[2] = 0;
self.machine->set_processor_state(state);
self.machine->run_for_instructions(1);

10
OSBindings/Mac/Clock SignalTests/Comparative68000.hpp
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@ -11,9 +11,9 @@
#include <zlib.h>
#include "68000.hpp"
#include "68000Mk2.hpp"
class ComparativeBusHandler: public CPU::MC68000::BusHandler {
class ComparativeBusHandler: public CPU::MC68000Mk2::BusHandler {
public:
ComparativeBusHandler(const char *trace_name) {
trace = gzopen(trace_name, "rt");
@ -30,14 +30,14 @@ class ComparativeBusHandler: public CPU::MC68000::BusHandler {
++line_count;
// Generate state locally.
const auto state = get_state();
const auto state = get_state().registers;
char local_state[300];
sprintf(local_state, "%04x: %02x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x\n",
address,
state.status,
state.data[0], state.data[1], state.data[2], state.data[3], state.data[4], state.data[5], state.data[6], state.data[7],
state.address[0], state.address[1], state.address[2], state.address[3], state.address[4], state.address[5], state.address[6],
(state.status & 0x2000) ? state.supervisor_stack_pointer : state.user_stack_pointer
state.stack_pointer()
);
// Check that the two coincide.
@ -49,7 +49,7 @@ class ComparativeBusHandler: public CPU::MC68000::BusHandler {
}
}
virtual CPU::MC68000::ProcessorState get_state() = 0;
virtual CPU::MC68000Mk2::State get_state() = 0;
private:
int line_count = 0;

18
OSBindings/Mac/Clock SignalTests/EmuTOSTests.mm
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@ -13,7 +13,7 @@
//#define LOG_TRACE
#include "68000.hpp"
#include "68000Mk2.hpp"
#include "Comparative68000.hpp"
#include "CSROMFetcher.hpp"
@ -32,11 +32,11 @@ class EmuTOS: public ComparativeBusHandler {
m68000_.run_for(cycles);
}
CPU::MC68000::ProcessorState get_state() final {
CPU::MC68000Mk2::State get_state() final {
return m68000_.get_state();
}
HalfCycles perform_bus_operation(const CPU::MC68000::Microcycle &cycle, int) {
HalfCycles perform_bus_operation(const CPU::MC68000Mk2::Microcycle &cycle, int) {
const uint32_t address = cycle.word_address();
uint32_t word_address = address;
@ -56,7 +56,7 @@ class EmuTOS: public ComparativeBusHandler {
word_address %= ram_.size();
}
using Microcycle = CPU::MC68000::Microcycle;
using Microcycle = CPU::MC68000Mk2::Microcycle;
if(cycle.data_select_active()) {
uint16_t peripheral_result = 0xffff;
if(is_peripheral) {
@ -72,16 +72,16 @@ class EmuTOS: public ComparativeBusHandler {
default: break;
case Microcycle::SelectWord | Microcycle::Read:
cycle.value->full = is_peripheral ? peripheral_result : base[word_address];
cycle.value->w = is_peripheral ? peripheral_result : base[word_address];
break;
case Microcycle::SelectByte | Microcycle::Read:
cycle.value->halves.low = (is_peripheral ? peripheral_result : base[word_address]) >> cycle.byte_shift();
cycle.value->b = (is_peripheral ? peripheral_result : base[word_address]) >> cycle.byte_shift();
break;
case Microcycle::SelectWord:
base[word_address] = cycle.value->full;
base[word_address] = cycle.value->w;
break;
case Microcycle::SelectByte:
base[word_address] = (cycle.value->halves.low << cycle.byte_shift()) | (base[word_address] & (0xffff ^ cycle.byte_mask()));
base[word_address] = (cycle.value->b << cycle.byte_shift()) | (base[word_address] & (0xffff ^ cycle.byte_mask()));
break;
}
}
@ -90,7 +90,7 @@ class EmuTOS: public ComparativeBusHandler {
}
private:
CPU::MC68000::Processor<EmuTOS, true, true> m68000_;
CPU::MC68000Mk2::Processor<EmuTOS, true, true> m68000_;
std::vector<uint16_t> emuTOS_;
std::array<uint16_t, 256*1024> ram_;

16
OSBindings/Mac/Clock SignalTests/QLTests.mm
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@ -35,11 +35,11 @@ class QL: public ComparativeBusHandler {
m68000_.run_for(cycles);
}
CPU::MC68000::ProcessorState get_state() final {
CPU::MC68000Mk2::State get_state() final {
return m68000_.get_state();
}
HalfCycles perform_bus_operation(const CPU::MC68000::Microcycle &cycle, int) {
HalfCycles perform_bus_operation(const CPU::MC68000Mk2::Microcycle &cycle, int) {
const uint32_t address = cycle.word_address();
uint32_t word_address = address;
@ -56,7 +56,7 @@ class QL: public ComparativeBusHandler {
word_address %= ram_.size();
}
using Microcycle = CPU::MC68000::Microcycle;
using Microcycle = CPU::MC68000Mk2::Microcycle;
if(cycle.data_select_active()) {
uint16_t peripheral_result = 0xffff;
@ -64,18 +64,18 @@ class QL: public ComparativeBusHandler {
default: break;
case Microcycle::SelectWord | Microcycle::Read:
cycle.value->full = is_peripheral ? peripheral_result : base[word_address];
cycle.value->w = is_peripheral ? peripheral_result : base[word_address];
break;
case Microcycle::SelectByte | Microcycle::Read:
cycle.value->halves.low = (is_peripheral ? peripheral_result : base[word_address]) >> cycle.byte_shift();
cycle.value->b = (is_peripheral ? peripheral_result : base[word_address]) >> cycle.byte_shift();
break;
case Microcycle::SelectWord:
assert(!(is_rom && !is_peripheral));
if(!is_peripheral) base[word_address] = cycle.value->full;
if(!is_peripheral) base[word_address] = cycle.value->w;
break;
case Microcycle::SelectByte:
assert(!(is_rom && !is_peripheral));
if(!is_peripheral) base[word_address] = (cycle.value->halves.low << cycle.byte_shift()) | (base[word_address] & (0xffff ^ cycle.byte_mask()));
if(!is_peripheral) base[word_address] = (cycle.value->b << cycle.byte_shift()) | (base[word_address] & (0xffff ^ cycle.byte_mask()));
break;
}
}
@ -84,7 +84,7 @@ class QL: public ComparativeBusHandler {
}
private:
CPU::MC68000::Processor<QL, true, true> m68000_;
CPU::MC68000Mk2::Processor<QL, true, false, true> m68000_;
std::vector<uint16_t> rom_;
std::array<uint16_t, 64*1024> ram_;