From 2cac4b0d748668d1004bad414d58334c209815a3 Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Fri, 19 Apr 2019 23:02:41 -0400 Subject: [PATCH] Corrects EA usage for ADDA and SUBA. --- OSBindings/Mac/Clock SignalTests/QLTests.mm | 8 ++++---- Processors/68000/Implementation/68000Implementation.hpp | 2 ++ Processors/68000/Implementation/68000Storage.cpp | 8 ++++---- 3 files changed, 10 insertions(+), 8 deletions(-) diff --git a/OSBindings/Mac/Clock SignalTests/QLTests.mm b/OSBindings/Mac/Clock SignalTests/QLTests.mm index 21f378f69..c7d902561 100644 --- a/OSBindings/Mac/Clock SignalTests/QLTests.mm +++ b/OSBindings/Mac/Clock SignalTests/QLTests.mm @@ -71,20 +71,20 @@ class QL: public CPU::MC68000::BusHandler { case Microcycle::SelectWord | Microcycle::Read: cycle.value->full = is_peripheral ? peripheral_result : base[word_address]; -// if(!(cycle.operation & Microcycle::IsProgram)) printf("[word r %08x -> %04x] ", *cycle.address, cycle.value->full); + if(!(cycle.operation & Microcycle::IsProgram)) printf("[word r %08x -> %04x]\n ", *cycle.address, cycle.value->full); break; case Microcycle::SelectByte | Microcycle::Read: cycle.value->halves.low = (is_peripheral ? peripheral_result : base[word_address]) >> cycle.byte_shift(); -// if(!(cycle.operation & Microcycle::IsProgram)) printf("[byte r %08x -> %02x] ", *cycle.address, cycle.value->halves.low); + if(!(cycle.operation & Microcycle::IsProgram)) printf("[byte r %08x -> %02x]\n", *cycle.address, cycle.value->halves.low); break; case Microcycle::SelectWord: assert(!(is_rom && !is_peripheral)); -// if(!(cycle.operation & Microcycle::IsProgram)) printf("[word w %04x -> %08x] ", cycle.value->full, *cycle.address); + if(!(cycle.operation & Microcycle::IsProgram)) printf("[word w %04x -> %08x]\n", cycle.value->full, *cycle.address); if(!is_peripheral) base[word_address] = cycle.value->full; break; case Microcycle::SelectByte: assert(!(is_rom && !is_peripheral)); -// if(!(cycle.operation & Microcycle::IsProgram)) printf("[byte w %02x -> %08x] ", cycle.value->halves.low, *cycle.address); + if(!(cycle.operation & Microcycle::IsProgram)) printf("[byte w %02x -> %08x]\n", cycle.value->halves.low, *cycle.address); if(!is_peripheral) base[word_address] = (cycle.value->halves.low << cycle.byte_shift()) | (base[word_address] & (0xffff ^ cycle.byte_mask())); break; } diff --git a/Processors/68000/Implementation/68000Implementation.hpp b/Processors/68000/Implementation/68000Implementation.hpp index b34524dda..6518bafc5 100644 --- a/Processors/68000/Implementation/68000Implementation.hpp +++ b/Processors/68000/Implementation/68000Implementation.hpp @@ -63,6 +63,8 @@ template void Processor: should_log |= program_counter_.full > 0x286; if(should_log) { + std::cout << "a5:" << std::setw(8) << std::setfill('0') << address_[5].full << " "; + std::cout << "a6:" << std::setw(8) << std::setfill('0') << address_[6].full << " "; std::cout << "a7:" << std::setw(8) << std::setfill('0') << address_[7].full << " "; if(is_supervisor_) { std::cout << "usp:" << std::setw(8) << std::setfill('0') << stack_pointers_[0].full << " "; diff --git a/Processors/68000/Implementation/68000Storage.cpp b/Processors/68000/Implementation/68000Storage.cpp index c0cf86422..b11040146 100644 --- a/Processors/68000/Implementation/68000Storage.cpp +++ b/Processors/68000/Implementation/68000Storage.cpp @@ -1272,14 +1272,14 @@ struct ProcessorStorageConstructor { case bw(d16An): // ADDA/SUBA.w (d16, An), An case bw(d8AnXn): // ADDA/SUBA.w (d8, An, Xn), An op( calc_action_for_mode(mode) | MicroOp::SourceMask, - seq(pseq("np nr np nn", mode), { ea(1) })); + seq(pseq("np nr np nn", mode), { ea(0) })); op(Action::PerformOperation); break; case l(d16An): // ADDA/SUBA.l (d16, An), An case l(d8AnXn): // ADDA/SUBA.l (d8, An, Xn), An op( calc_action_for_mode(mode) | MicroOp::SourceMask, - seq(pseq("np nR+ nr np n", mode), { ea(1), ea(1) })); + seq(pseq("np nR+ nr np n", mode), { ea(0), ea(0) })); op(Action::PerformOperation); break; @@ -1287,7 +1287,7 @@ struct ProcessorStorageConstructor { op(Action::None, seq("np")); case bw(XXXw): // ADDA/SUBA.w (xxx).w, An op( address_assemble_for_mode(mode) | MicroOp::SourceMask, - seq("np nr np nn", { ea(1) })); + seq("np nr np nn", { ea(0) })); op(Action::PerformOperation); break; @@ -1295,7 +1295,7 @@ struct ProcessorStorageConstructor { op(Action::None, seq("np")); case l(XXXw): // ADDA/SUBA.l (xxx).w, An op( address_assemble_for_mode(mode) | MicroOp::SourceMask, - seq("np nR+ nr np n", { ea(1), ea(1) })); + seq("np nR+ nr np n", { ea(0), ea(0) })); op( Action::PerformOperation); break;