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Adds BTST.
This commit is contained in:
Thomas Harte
parent
068ce23716
commit
2d153359f8
@ -147,6 +147,16 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
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}
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}
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} break;
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} break;
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// Two BTSTs: set the zero flag according to the value of the destination masked by
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// the bit named in the source modulo the operation size.
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case Operation::BTSTb:
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zero_result_ = active_program_->destination->full & (1 << (active_program_->source->full & 7));
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break;
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case Operation::BTSTl:
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zero_result_ = active_program_->destination->full & (1 << (active_program_->source->full & 31));
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break;
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// Bcc: evaluates the relevant condition and displacement size and then:
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// Bcc: evaluates the relevant condition and displacement size and then:
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// if condition is false, schedules bus operations to get past this instruction;
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// if condition is false, schedules bus operations to get past this instruction;
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// otherwise applies the offset and schedules bus operations to refill the prefetch queue.
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// otherwise applies the offset and schedules bus operations to refill the prefetch queue.
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@ -266,6 +266,8 @@ struct ProcessorStorageConstructor {
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JMP, // six lowest bits are [mode, register], decoding to JMP
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JMP, // six lowest bits are [mode, register], decoding to JMP
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ADDSUB,
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ADDSUB,
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ADDASUBA,
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ADDASUBA,
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BTST, // bit 9,10,11 are register, six lowest bits are [mode, register], decoding to BTST
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BTSTIMM, // six lowest bits are [mode, register], decoding to BTST #
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};
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};
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using Operation = ProcessorStorage::Operation;
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using Operation = ProcessorStorage::Operation;
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@ -331,6 +333,9 @@ struct ProcessorStorageConstructor {
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{0xf1c0, 0xd1c0, Operation::ADDAl, Decoder::ADDASUBA}, // 4-7 (p111)
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{0xf1c0, 0xd1c0, Operation::ADDAl, Decoder::ADDASUBA}, // 4-7 (p111)
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{0xf1c0, 0x90c0, Operation::SUBAw, Decoder::ADDASUBA}, // 4-177 (p281)
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{0xf1c0, 0x90c0, Operation::SUBAw, Decoder::ADDASUBA}, // 4-177 (p281)
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{0xf1c0, 0x91c0, Operation::SUBAl, Decoder::ADDASUBA}, // 4-177 (p281)
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{0xf1c0, 0x91c0, Operation::SUBAl, Decoder::ADDASUBA}, // 4-177 (p281)
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{0xf1c0, 0x0100, Operation::BTSTb, Decoder::BTST}, // 4-62 (p166)
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{0xffc0, 0x0800, Operation::BTSTb, Decoder::BTSTIMM}, // 4-63 (p167)
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};
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};
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std::vector<size_t> micro_op_pointers(65536, std::numeric_limits<size_t>::max());
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std::vector<size_t> micro_op_pointers(65536, std::numeric_limits<size_t>::max());
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@ -686,6 +691,114 @@ struct ProcessorStorageConstructor {
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op(Action::PerformOperation, seq("n np np"));
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op(Action::PerformOperation, seq("n np np"));
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} break;
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} break;
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// Decodes a BTST, potential mutating the operation into a BTSTl.
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case Decoder::BTST: {
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const int mask_register = (instruction >> 9) & 7;
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storage_.instructions[instruction].set_source(storage_, 0, mask_register);
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storage_.instructions[instruction].set_destination(storage_, source_mode, source_register);
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const int mode = combined_mode(source_mode, source_register);
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switch(mode) {
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default: continue;
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case 0x00: // BTST.l Dn, Dn
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operation = Operation::BTSTl;
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op(Action::PerformOperation, seq("np n"));
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break;
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case 0x02: // BTST.b Dn, (An)
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case 0x03: // BTST.b Dn, (An)+
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op(Action::None, seq("nrd np", { &storage_.data_[source_register].full }, false));
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op(Action::PerformOperation);
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if(mode == 0x03) {
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op(int(Action::Increment1) | MicroOp::DestinationMask);
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}
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break;
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case 0x04: // BTST.b Dn, -(An)
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op(int(Action::Decrement1) | MicroOp::DestinationMask, seq("n nrd np", { &storage_.data_[source_register].full }, false));
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op(Action::PerformOperation);
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break;
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case 0x05: // BTST.b Dn, (d16, An)
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case 0x06: // BTST.b Dn, (d8, An, Xn)
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case 0x12: // BTST.b Dn, (d16, PC)
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case 0x13: // BTST.b Dn, (d8, PC, Xn)
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op( calc_action_for_mode(mode) | MicroOp::DestinationMask,
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seq(pseq("np nrd np", mode), { ea(1) }, false));
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op(Action::PerformOperation);
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break;
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case 0x10: // BTST.b Dn, (xxx).w
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op( int(Action::AssembleWordAddressFromPrefetch) | MicroOp::DestinationMask,
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seq("np nrd np", { ea(1) }, false));
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op(Action::PerformOperation);
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break;
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case 0x11: // BTST.b Dn, (xxx).l
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op(Action::None, seq("np"));
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op( int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask,
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seq("np nrd np", { ea(1) }, false));
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op(Action::PerformOperation);
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break;
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}
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} break;
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case Decoder::BTSTIMM: {
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storage_.instructions[instruction].source = &storage_.source_bus_data_[0];
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storage_.instructions[instruction].set_destination(storage_, source_mode, source_register);
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const int mode = combined_mode(source_mode, source_register);
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switch(mode) {
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default: continue;
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case 0x00: // BTST.l #, Dn
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operation = Operation::BTSTl;
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op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np np n"));
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op(Action::PerformOperation);
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break;
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case 0x02: // BTST.b #, (An)
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case 0x03: // BTST.b #, (An)+
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op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np nrd np", { &storage_.data_[source_register].full }, false));
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op(Action::PerformOperation);
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if(mode == 0x03) {
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op(int(Action::Increment1) | MicroOp::DestinationMask);
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}
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break;
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case 0x04: // BTST.b #, -(An)
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op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np"));
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op(int(Action::Decrement1) | MicroOp::DestinationMask, seq("n nrd np", { &storage_.data_[source_register].full }, false));
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op(Action::PerformOperation);
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break;
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case 0x05: // BTST.b #, (d16, An)
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case 0x06: // BTST.b #, (d8, An, Xn)
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case 0x12: // BTST.b #, (d16, PC)
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case 0x13: // BTST.b #, (d8, PC, Xn)
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op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np"));
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op( calc_action_for_mode(mode) | MicroOp::DestinationMask,
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seq(pseq("np nrd np", mode), { ea(1) }, false));
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op(Action::PerformOperation);
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break;
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case 0x10: // BTST.b #, (xxx).w
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op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np"));
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op( int(Action::AssembleWordAddressFromPrefetch) | MicroOp::DestinationMask,
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seq("np nrd np", { ea(1) }, false));
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op(Action::PerformOperation);
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break;
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case 0x11: // BTST.b #, (xxx).l
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op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np np"));
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op( int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask,
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seq("np nrd np", { ea(1) }, false));
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op(Action::PerformOperation);
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break;
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}
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} break;
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// Decodes the format used by ABCD and SBCD.
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// Decodes the format used by ABCD and SBCD.
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case Decoder::Decimal: {
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case Decoder::Decimal: {
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const int destination_register = (instruction >> 9) & 7;
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const int destination_register = (instruction >> 9) & 7;
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@ -57,8 +57,9 @@ class ProcessorStorage {
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MOVEtoSR, MOVEfromSR,
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MOVEtoSR, MOVEfromSR,
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CMPb, CMPw, CMPl,
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CMPb, CMPw, CMPl,
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BTSTb, BTSTl,
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BRA, Bcc, JMP
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BRA, Bcc, JMP,
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};
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};
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/*!
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/*!
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