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https://github.com/TomHarte/CLK.git
synced 2026-04-25 11:17:26 +00:00
Makes a more concrete attempt at track/sector combination.
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@@ -83,7 +83,7 @@ template <typename BitHandler, size_t length_of_history = 3> class DigitalPhaseL
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total_spacing_ -= offset_history_[offset_history_pointer_].spacing;
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// Fill in the new fields.
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const auto multiple = (new_offset + (clocks_per_bit_ >> 1)) / clocks_per_bit_;
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const auto multiple = std::max((new_offset + (clocks_per_bit_ >> 1)) / clocks_per_bit_, Cycles::IntType(1));
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offset_history_[offset_history_pointer_].divisor = multiple;
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offset_history_[offset_history_pointer_].spacing = new_offset;
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@@ -94,19 +94,19 @@ template <typename BitHandler, size_t length_of_history = 3> class DigitalPhaseL
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// Advance the write slot.
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offset_history_pointer_ = (offset_history_pointer_ + 1) % offset_history_.size();
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#ifndef NDEBUG
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Cycles::IntType td = 0, ts = 0;
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for(auto offset: offset_history_) {
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td += offset.divisor;
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ts += offset.spacing;
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}
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assert(ts == total_spacing_);
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assert(td == total_divisor_);
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#endif
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// In net: use an unweighted average of the stored offsets to compute current window size,
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// bucketing them by rounding to the nearest multiple of the base clocks per bit
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window_length_ = total_spacing_ / total_divisor_;
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#ifndef NDEBUG
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bool are_all_filled = true;
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for(auto offset: offset_history_) {
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if(offset.spacing == 1) {
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are_all_filled = false;
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break;
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}
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}
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assert(!are_all_filled || (window_length_ >= ((clocks_per_bit_ * 9) / 10) && window_length_ <= ((clocks_per_bit_ * 11) / 10)));
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#endif
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// Also apply a difference to phase, use a simple spring mechanism as a lowpass filter.
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const auto error = new_phase - (window_length_ >> 1);
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