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Attempts to provide a data out phase.

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Thomas Harte
2019-08-22 23:16:58 -04:00
parent faec516a2c
commit 2d82855f26
7 changed files with 150 additions and 19 deletions
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Components/5380/ncr5380.hpp
+2 -2
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@@ -12,7 +12,7 @@
#include <cstdint>
#include "../../Storage/MassStorage/SCSI/SCSI.hpp"
#include "../../Storage/MassStorage/SCSI/Target.hpp"
#include "../../Storage/MassStorage/SCSI/DirectAccessDevice.hpp"
#include "../../ClockReceiver/ClockReceiver.hpp"
#include "../../ClockReceiver/ClockingHintSource.hpp"
@@ -56,7 +56,7 @@ class NCR5380 final: public ClockingHint::Source {
// TEMPORARY. For development expediency, the 5380 owns its own
// SCSI bus and target. These will be moved out.
SCSI::Bus bus_;
SCSI::Target::Target<SCSI::Target::Executor> device_;
SCSI::Target::Target<SCSI::DirectAccessDevice> device_;
const int clock_rate_;
size_t device_id_;