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Implement MOVEP.

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This commit is contained in:
Thomas Harte
2022-05-20 14:22:32 -04:00
parent 81431a5453
commit 2d91fb5441
3 changed files with 115 additions and 2 deletions
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5
OSBindings/Mac/Clock SignalTests/68000ComparativeTests.mm
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@@ -156,7 +156,7 @@ struct TestProcessor: public CPU::MC68000Mk2::BusHandler {
// To limit tests run to a subset of files and/or of tests, uncomment and fill in below. // To limit tests run to a subset of files and/or of tests, uncomment and fill in below.
_fileSet = [NSSet setWithArray:@[ _fileSet = [NSSet setWithArray:@[
@"btst_bchg_bclr_bset.json", // @"btst_bchg_bclr_bset.json",
// Below this line are passing tests. // Below this line are passing tests.
@"abcd_sbcd.json", @"abcd_sbcd.json",
@@ -169,10 +169,11 @@ struct TestProcessor: public CPU::MC68000Mk2::BusHandler {
@"dbcc_scc.json", @"dbcc_scc.json",
@"eor_and_or.json", @"eor_and_or.json",
@"ext.json", @"ext.json",
@"movep.json",
@"nbcd.json", @"nbcd.json",
@"ext.json", @"ext.json",
@"swap.json", @"swap.json",
]]; // 13/32 = ~41 % done, as far as the tests go. ]]; // 14/32 = ~44 % done, as far as the tests go.
// _testSet = [NSSet setWithArray:@[@"ADDQ 05df"]]; // _testSet = [NSSet setWithArray:@[@"ADDQ 05df"]];
} }

108
Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
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@@ -101,6 +101,11 @@ enum ExecutionState: int {
BCHG_BSET_Dn, BCHG_BSET_Dn,
BCLR_Dn, BCLR_Dn,
MOVEPtoM_w,
MOVEPtoM_l,
MOVEPtoR_w,
MOVEPtoR_l,
}; };
// MARK: - The state machine. // MARK: - The state machine.
@@ -576,6 +581,22 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
} }
}); });
StdCASE(MOVEPl, {
if(instruction_.mode(0) == Mode::DataRegisterDirect) {
MoveToState(MOVEPtoM_l);
} else {
MoveToState(MOVEPtoR_l);
}
});
StdCASE(MOVEPw, {
if(instruction_.mode(0) == Mode::DataRegisterDirect) {
MoveToState(MOVEPtoM_w);
} else {
MoveToState(MOVEPtoR_w);
}
});
default: default:
assert(false); assert(false);
} }
@@ -1276,6 +1297,93 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
registers_[instruction_.reg(1)] = operand_[1]; registers_[instruction_.reg(1)] = operand_[1];
MoveToState(Decode); MoveToState(Decode);
//
// MOVEP
//
BeginState(MOVEPtoM_l):
temporary_address_.l = registers_[8 + instruction_.reg(1)].l + uint32_t(int16_t(prefetch_.w));
SetDataAddress(temporary_address_.l);
SetupDataAccess(0, Microcycle::SelectByte);
Prefetch(); // np
temporary_value_.b = uint8_t(registers_[instruction_.reg(0)].l >> 24);
Access(temporary_value_.low); // nW
temporary_address_.l += 2;
temporary_value_.b = uint8_t(registers_[instruction_.reg(0)].l >> 16);
Access(temporary_value_.low); // nW
temporary_address_.l += 2;
temporary_value_.b = uint8_t(registers_[instruction_.reg(0)].l >> 8);
Access(temporary_value_.low); // nw
temporary_address_.l += 2;
temporary_value_.b = uint8_t(registers_[instruction_.reg(0)].l);
Access(temporary_value_.low); // nw
Prefetch(); // np
MoveToState(Decode);
BeginState(MOVEPtoM_w):
temporary_address_.l = registers_[8 + instruction_.reg(1)].l + uint32_t(int16_t(prefetch_.w));
SetDataAddress(temporary_address_.l);
SetupDataAccess(0, Microcycle::SelectByte);
Prefetch(); // np
temporary_value_.b = uint8_t(registers_[instruction_.reg(0)].l >> 8);
Access(temporary_value_.low); // nW
temporary_address_.l += 2;
temporary_value_.b = uint8_t(registers_[instruction_.reg(0)].l);
Access(temporary_value_.low); // nw
Prefetch(); // np
MoveToState(Decode);
BeginState(MOVEPtoR_l):
temporary_address_.l = registers_[8 + instruction_.reg(0)].l + uint32_t(int16_t(prefetch_.w));
SetDataAddress(temporary_address_.l);
SetupDataAccess(Microcycle::Read, Microcycle::SelectByte);
Prefetch(); // np
Access(temporary_value_.low); // nR
registers_[instruction_.reg(1)].l = temporary_value_.b << 24;
temporary_address_.l += 2;
Access(temporary_value_.low); // nR
registers_[instruction_.reg(1)].w |= temporary_value_.b << 16;
temporary_address_.l += 2;
Access(temporary_value_.low); // nr
registers_[instruction_.reg(1)].w |= temporary_value_.b << 8;
temporary_address_.l += 2;
Access(temporary_value_.low); // nr
registers_[instruction_.reg(1)].w |= temporary_value_.b;
Prefetch(); // np
MoveToState(Decode);
BeginState(MOVEPtoR_w):
temporary_address_.l = registers_[8 + instruction_.reg(0)].l + uint32_t(int16_t(prefetch_.w));
SetDataAddress(temporary_address_.l);
SetupDataAccess(Microcycle::Read, Microcycle::SelectByte);
Prefetch(); // np
Access(temporary_value_.low); // nR
registers_[instruction_.reg(1)].w = temporary_value_.b << 8;
temporary_address_.l += 2;
Access(temporary_value_.low); // nr
registers_[instruction_.reg(1)].w |= temporary_value_.b;
Prefetch(); // np
MoveToState(Decode);
// //
// Various states TODO. // Various states TODO.
// //

4
Processors/68000Mk2/Implementation/68000Mk2Storage.hpp
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@@ -81,6 +81,10 @@ struct ProcessorBase: public InstructionSet::M68k::NullFlowController {
/// a data select). /// a data select).
SlicedInt32 temporary_address_; SlicedInt32 temporary_address_;
/// Storage for a temporary value; primarily used by MOVEP to split a 32-bit
/// source into bus-compatible byte units.
SlicedInt32 temporary_value_;
/// A record of the exception to trigger. /// A record of the exception to trigger.
int exception_vector_ = 0; int exception_vector_ = 0;