mirror of
https://github.com/TomHarte/CLK.git
synced 2024-11-23 03:32:32 +00:00
Merge branch 'master' of github.com:TomHarte/CLK
This commit is contained in:
Thomas Harte
commit
2d9dd6704a
@ -128,13 +128,14 @@ template <class T> class MOS6522: public MOS6522Storage {
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void access(int address);
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uint8_t get_port_input(Port port, uint8_t output_mask, uint8_t output);
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uint8_t get_port_input(Port port, uint8_t output_mask, uint8_t output, uint8_t timer_mask);
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inline void reevaluate_interrupts();
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/// Sets the current intended output value for the port and line;
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/// if this affects the visible output, it will be passed to the handler.
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void set_control_line_output(Port port, Line line, LineState value);
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void evaluate_cb2_output();
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void evaluate_port_b_output();
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};
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}
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@ -8,6 +8,10 @@
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#include "../../../Outputs/Log.hpp"
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// As-yet unimplemented (incomplete list):
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//
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// PB6 count-down mode for timer 2.
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namespace MOS {
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namespace MOS6522 {
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@ -34,18 +38,18 @@ template <typename T> void MOS6522<T>::write(int address, uint8_t value) {
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address &= 0xf;
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access(address);
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switch(address) {
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case 0x0: // Write Port B.
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case 0x0: // Write Port B. ('ORB')
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// Store locally and communicate outwards.
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registers_.output[1] = value;
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bus_handler_.run_for(time_since_bus_handler_call_.flush<HalfCycles>());
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bus_handler_.set_port_output(Port::B, value, registers_.data_direction[1]);
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evaluate_port_b_output();
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registers_.interrupt_flags &= ~(InterruptFlag::CB1ActiveEdge | ((registers_.peripheral_control&0x20) ? 0 : InterruptFlag::CB2ActiveEdge));
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reevaluate_interrupts();
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break;
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case 0xf:
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case 0x1: // Write Port A.
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case 0x1: // Write Port A. ('ORA')
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registers_.output[0] = value;
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bus_handler_.run_for(time_since_bus_handler_call_.flush<HalfCycles>());
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@ -59,28 +63,44 @@ template <typename T> void MOS6522<T>::write(int address, uint8_t value) {
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reevaluate_interrupts();
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break;
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case 0x2: // Port B direction.
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case 0x2: // Port B direction ('DDRB').
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registers_.data_direction[1] = value;
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break;
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case 0x3: // Port A direction.
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case 0x3: // Port A direction ('DDRA').
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registers_.data_direction[0] = value;
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break;
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// Timer 1
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case 0x6: case 0x4: registers_.timer_latch[0] = (registers_.timer_latch[0]&0xff00) | value; break;
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case 0x5: case 0x7:
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case 0x6: case 0x4: // ('T1L-L' and 'T1C-L')
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registers_.timer_latch[0] = (registers_.timer_latch[0]&0xff00) | value;
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break;
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case 0x7: // Timer 1 latch, high ('T1L-H').
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registers_.timer_latch[0] = (registers_.timer_latch[0]&0x00ff) | uint16_t(value << 8);
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registers_.interrupt_flags &= ~InterruptFlag::Timer1;
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if(address == 0x05) {
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break;
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case 0x5: // Timer 1 counter, high ('T1C-H').
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// Fill latch.
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registers_.timer_latch[0] = (registers_.timer_latch[0]&0x00ff) | uint16_t(value << 8);
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// Restart timer.
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registers_.next_timer[0] = registers_.timer_latch[0];
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timer_is_running_[0] = true;
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// If PB7 output mode is active, set it low.
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if(registers_.auxiliary_control & 0x80) {
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registers_.timer_port_b_output &= 0x7f;
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evaluate_port_b_output();
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}
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// Clear existing interrupt flag.
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registers_.interrupt_flags &= ~InterruptFlag::Timer1;
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reevaluate_interrupts();
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break;
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// Timer 2
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case 0x8: registers_.timer_latch[1] = value; break;
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case 0x9:
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case 0x8: // ('T2C-L')
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registers_.timer_latch[1] = value;
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break;
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case 0x9: // ('T2C-H')
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registers_.interrupt_flags &= ~InterruptFlag::Timer2;
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registers_.next_timer[1] = registers_.timer_latch[1] | uint16_t(value << 8);
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timer_is_running_[1] = true;
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@ -88,7 +108,7 @@ template <typename T> void MOS6522<T>::write(int address, uint8_t value) {
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break;
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// Shift
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case 0xa:
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case 0xa: // ('SR')
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registers_.shift = value;
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shift_bits_remaining_ = 8;
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registers_.interrupt_flags &= ~InterruptFlag::ShiftRegister;
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@ -96,11 +116,18 @@ template <typename T> void MOS6522<T>::write(int address, uint8_t value) {
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break;
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// Control
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case 0xb:
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case 0xb: // Auxiliary control ('ACR').
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registers_.auxiliary_control = value;
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evaluate_cb2_output();
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// This is a bit of a guess: reset the timer-based PB7 output to its default high level
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// any timer that timer-linked PB7 output is disabled.
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if(!(registers_.auxiliary_control & 0x80)) {
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registers_.timer_port_b_output |= 0x80;
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}
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evaluate_port_b_output();
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break;
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case 0xc: {
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case 0xc: { // Peripheral control ('PCR').
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// const auto old_peripheral_control = registers_.peripheral_control;
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registers_.peripheral_control = value;
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@ -141,11 +168,11 @@ template <typename T> void MOS6522<T>::write(int address, uint8_t value) {
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} break;
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// Interrupt control
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case 0xd:
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case 0xd: // Interrupt flag regiser ('IFR').
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registers_.interrupt_flags &= ~value;
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reevaluate_interrupts();
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break;
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case 0xe:
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case 0xe: // Interrupt enable register ('IER').
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if(value&0x80)
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registers_.interrupt_enable |= value;
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else
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@ -159,54 +186,55 @@ template <typename T> uint8_t MOS6522<T>::read(int address) {
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address &= 0xf;
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access(address);
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switch(address) {
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case 0x0:
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case 0x0: // Read Port B ('IRB').
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registers_.interrupt_flags &= ~(InterruptFlag::CB1ActiveEdge | InterruptFlag::CB2ActiveEdge);
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reevaluate_interrupts();
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return get_port_input(Port::B, registers_.data_direction[1], registers_.output[1]);
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return get_port_input(Port::B, registers_.data_direction[1], registers_.output[1], registers_.auxiliary_control & 0x80);
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case 0xf:
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case 0x1:
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case 0x1: // Read Port A ('IRA').
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registers_.interrupt_flags &= ~(InterruptFlag::CA1ActiveEdge | InterruptFlag::CA2ActiveEdge);
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reevaluate_interrupts();
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return get_port_input(Port::A, registers_.data_direction[0], registers_.output[0]);
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return get_port_input(Port::A, registers_.data_direction[0], registers_.output[0], 0);
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case 0x2: return registers_.data_direction[1];
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case 0x3: return registers_.data_direction[0];
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case 0x2: return registers_.data_direction[1]; // Port B direction ('DDRB').
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case 0x3: return registers_.data_direction[0]; // Port A direction ('DDRA').
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// Timer 1
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case 0x4:
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case 0x4: // Timer 1 low-order latches ('T1L-L').
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registers_.interrupt_flags &= ~InterruptFlag::Timer1;
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reevaluate_interrupts();
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return registers_.timer[0] & 0x00ff;
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case 0x5: return registers_.timer[0] >> 8;
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case 0x6: return registers_.timer_latch[0] & 0x00ff;
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case 0x7: return registers_.timer_latch[0] >> 8;
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case 0x5: return registers_.timer[0] >> 8; // Timer 1 high-order counter ('T1C-H')
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case 0x6: return registers_.timer_latch[0] & 0x00ff; // Timer 1 low-order latches ('T1L-L').
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case 0x7: return registers_.timer_latch[0] >> 8; // Timer 1 high-order latches ('T1L-H').
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// Timer 2
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case 0x8:
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case 0x8: // Timer 2 low-order counter ('T2C-L').
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registers_.interrupt_flags &= ~InterruptFlag::Timer2;
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reevaluate_interrupts();
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return registers_.timer[1] & 0x00ff;
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case 0x9: return registers_.timer[1] >> 8;
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case 0x9: return registers_.timer[1] >> 8; // Timer 2 high-order counter ('T2C-H').
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case 0xa:
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case 0xa: // Shift register ('SR').
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shift_bits_remaining_ = 8;
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registers_.interrupt_flags &= ~InterruptFlag::ShiftRegister;
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reevaluate_interrupts();
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return registers_.shift;
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case 0xb: return registers_.auxiliary_control;
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case 0xc: return registers_.peripheral_control;
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case 0xb: return registers_.auxiliary_control; // Auxiliary control ('ACR').
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case 0xc: return registers_.peripheral_control; // Peripheral control ('PCR').
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case 0xd: return registers_.interrupt_flags | (get_interrupt_line() ? 0x80 : 0x00);
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case 0xe: return registers_.interrupt_enable | 0x80;
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case 0xd: return registers_.interrupt_flags | (get_interrupt_line() ? 0x80 : 0x00); // Interrupt flag register ('IFR').
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case 0xe: return registers_.interrupt_enable | 0x80; // Interrupt enable register ('IER').
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}
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return 0xff;
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}
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template <typename T> uint8_t MOS6522<T>::get_port_input(Port port, uint8_t output_mask, uint8_t output) {
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template <typename T> uint8_t MOS6522<T>::get_port_input(Port port, uint8_t output_mask, uint8_t output, uint8_t timer_mask) {
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bus_handler_.run_for(time_since_bus_handler_call_.flush<HalfCycles>());
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const uint8_t input = bus_handler_.get_port_input(port);
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output = (output & ~timer_mask) | (registers_.timer_port_b_output & timer_mask);
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return (input & ~output_mask) | (output & output_mask);
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}
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@ -276,10 +304,13 @@ template <typename T> void MOS6522<T>::do_phase2() {
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registers_.timer_needs_reload = false;
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registers_.timer[0] = registers_.timer_latch[0];
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} else {
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registers_.timer[0] --;
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-- registers_.timer[0];
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}
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registers_.timer[1] --;
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// Count down timer 2 if it is in timed interrupt mode (i.e. auxiliary control bit 5 is clear).
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// TODO: implement count down on PB6 if this bit isn't set.
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registers_.timer[1] -= 1 ^ ((registers_.auxiliary_control >> 5)&1);
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if(registers_.next_timer[0] >= 0) {
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registers_.timer[0] = uint16_t(registers_.next_timer[0]);
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registers_.next_timer[0] = -1;
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@ -337,13 +368,22 @@ template <typename T> void MOS6522<T>::do_phase1() {
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// Determine whether to toggle PB7.
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if(registers_.auxiliary_control&0x80) {
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registers_.output[1] ^= 0x80;
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registers_.timer_port_b_output ^= 0x80;
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bus_handler_.run_for(time_since_bus_handler_call_.flush<HalfCycles>());
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bus_handler_.set_port_output(Port::B, registers_.output[1], registers_.data_direction[1]);
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evaluate_port_b_output();
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}
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}
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}
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template <typename T> void MOS6522<T>::evaluate_port_b_output() {
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// Apply current timer-linked PB7 output if any atop the stated output.
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const uint8_t timer_control_bit = registers_.auxiliary_control & 0x80;
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bus_handler_.set_port_output(
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Port::B,
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(registers_.output[1] & (0xff ^ timer_control_bit)) | timer_control_bit,
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registers_.data_direction[1] | timer_control_bit);
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}
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/*! Runs for a specified number of half cycles. */
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template <typename T> void MOS6522<T>::run_for(const HalfCycles half_cycles) {
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auto number_of_half_cycles = half_cycles.as_integral();
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@ -34,7 +34,9 @@ class MOS6522Storage {
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uint8_t peripheral_control = 0;
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uint8_t interrupt_flags = 0;
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uint8_t interrupt_enable = 0;
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bool timer_needs_reload = false;
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uint8_t timer_port_b_output = 0xff;
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} registers_;
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// Control state.
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@ -860,6 +860,7 @@
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||||
4BEF6AAC1D35D1C400E73575 /* DPLLTests.swift in Sources */ = {isa = PBXBuildFile; fileRef = 4BEF6AAB1D35D1C400E73575 /* DPLLTests.swift */; };
|
||||
4BF437EE209D0F7E008CBD6B /* SegmentParser.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4BF437EC209D0F7E008CBD6B /* SegmentParser.cpp */; };
|
||||
4BF437EF209D0F7E008CBD6B /* SegmentParser.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4BF437EC209D0F7E008CBD6B /* SegmentParser.cpp */; };
|
||||
4BF8D4C82516E27A00BBE21B /* Accelerate.framework in Frameworks */ = {isa = PBXBuildFile; fileRef = 4BB8617024E22F4900A00E03 /* Accelerate.framework */; };
|
||||
4BFCA1241ECBDCB400AC40C1 /* AllRAMProcessor.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4BFCA1211ECBDCAF00AC40C1 /* AllRAMProcessor.cpp */; };
|
||||
4BFCA1271ECBE33200AC40C1 /* TestMachineZ80.mm in Sources */ = {isa = PBXBuildFile; fileRef = 4BFCA1261ECBE33200AC40C1 /* TestMachineZ80.mm */; };
|
||||
4BFCA1291ECBE7A700AC40C1 /* zexall.com in Resources */ = {isa = PBXBuildFile; fileRef = 4BFCA1281ECBE7A700AC40C1 /* zexall.com */; };
|
||||
@ -1830,6 +1831,7 @@
|
||||
buildActionMask = 2147483647;
|
||||
files = (
|
||||
4B9F11CA2272433900701480 /* libz.tbd in Frameworks */,
|
||||
4BF8D4C82516E27A00BBE21B /* Accelerate.framework in Frameworks */,
|
||||
);
|
||||
runOnlyForDeploymentPostprocessing = 0;
|
||||
};
|
||||
|
||||
@ -101,6 +101,116 @@ class MOS6522Tests: XCTestCase {
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||||
}
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||||
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// MARK: PB7 timer 1 tests
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// These follow the same logic and check for the same results as the VICE VIC-20 via_pb7 tests.
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// Perfoms:
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//
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// (1) establish initial ACR and port B output value, and grab port B input value.
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// (2) start timer 1, grab port B input value.
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// (3) set final ACR, grab port B input value.
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// (4) allow timer 1 to expire, grab port B input value.
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private func runTest(startACR: UInt8, endACR: UInt8, portBOutput: UInt8) -> [UInt8] {
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var result: [UInt8] = []
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// Clear all register values.
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for n: UInt in 0...15 {
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m6522.setValue(0, forRegister: n)
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}
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m6522.run(forHalfCycles: 2)
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// Set data direction and current port B value.
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m6522.setValue(0xff, forRegister: 2)
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m6522.run(forHalfCycles: 2)
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m6522.setValue(portBOutput, forRegister: 0)
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m6522.run(forHalfCycles: 2)
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// Set initial ACR and grab the current port B value.
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m6522.setValue(startACR, forRegister: 0xb)
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m6522.run(forHalfCycles: 2)
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result.append(m6522.value(forRegister: 0))
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m6522.run(forHalfCycles: 2)
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// Start timer 1 and grab the value.
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m6522.setValue(1, forRegister: 0x5)
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m6522.run(forHalfCycles: 2)
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result.append(m6522.value(forRegister: 0))
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m6522.run(forHalfCycles: 2)
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// Set the final ACR value and grab value.
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m6522.setValue(endACR, forRegister: 0xb)
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m6522.run(forHalfCycles: 2)
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result.append(m6522.value(forRegister: 0))
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m6522.run(forHalfCycles: 2)
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// Make sure timer 1 has expired.
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m6522.run(forHalfCycles: 512)
|
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|
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// Grab the final value.
|
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result.append(m6522.value(forRegister: 0))
|
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|
||||
return result
|
||||
}
|
||||
|
||||
func testTimer1PB7() {
|
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// Original top row. [original Vic-20 screen output in comments on the right]
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XCTAssertEqual(runTest(startACR: 0x00, endACR: 0x00, portBOutput: 0x00), [0x00, 0x00, 0x00, 0x00]) // @@@@ (i.e. 0, 0, 0, 0)
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XCTAssertEqual(runTest(startACR: 0x00, endACR: 0x40, portBOutput: 0x00), [0x00, 0x00, 0x00, 0x00]) // @@@@ (i.e. 0, 0, 0, 0)
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XCTAssertEqual(runTest(startACR: 0x00, endACR: 0x80, portBOutput: 0x00), [0x00, 0x00, 0x80, 0x00]) // @@b@ (i.e. 0, 0, 1, 0)
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XCTAssertEqual(runTest(startACR: 0x00, endACR: 0xc0, portBOutput: 0x00), [0x00, 0x00, 0x80, 0x00]) // @@b@ (i.e. 0, 0, 1, 0)
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XCTAssertEqual(runTest(startACR: 0x00, endACR: 0x00, portBOutput: 0xff), [0xff, 0xff, 0xff, 0xff]) // cccc (i.e. 1, 1, 1, 1)
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XCTAssertEqual(runTest(startACR: 0x00, endACR: 0x40, portBOutput: 0xff), [0xff, 0xff, 0xff, 0xff]) // cccc (i.e. 1, 1, 1, 1)
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XCTAssertEqual(runTest(startACR: 0x00, endACR: 0x80, portBOutput: 0xff), [0xff, 0xff, 0xff, 0x7f]) // ccca (i.e. 1, 1, 1, 0)
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XCTAssertEqual(runTest(startACR: 0x00, endACR: 0xc0, portBOutput: 0xff), [0xff, 0xff, 0xff, 0x7f]) // ccca (i.e. 1, 1, 1, 0)
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||||
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// Second row. [same output as first row]
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||||
XCTAssertEqual(runTest(startACR: 0x40, endACR: 0x00, portBOutput: 0x00), [0x00, 0x00, 0x00, 0x00]) // @@@@
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XCTAssertEqual(runTest(startACR: 0x40, endACR: 0x40, portBOutput: 0x00), [0x00, 0x00, 0x00, 0x00]) // @@@@
|
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XCTAssertEqual(runTest(startACR: 0x40, endACR: 0x80, portBOutput: 0x00), [0x00, 0x00, 0x80, 0x00]) // @@b@
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||||
XCTAssertEqual(runTest(startACR: 0x40, endACR: 0xc0, portBOutput: 0x00), [0x00, 0x00, 0x80, 0x00]) // @@b@
|
||||
|
||||
XCTAssertEqual(runTest(startACR: 0x40, endACR: 0x00, portBOutput: 0xff), [0xff, 0xff, 0xff, 0xff]) // cccc
|
||||
XCTAssertEqual(runTest(startACR: 0x40, endACR: 0x40, portBOutput: 0xff), [0xff, 0xff, 0xff, 0xff]) // cccc
|
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XCTAssertEqual(runTest(startACR: 0x40, endACR: 0x80, portBOutput: 0xff), [0xff, 0xff, 0xff, 0x7f]) // ccca
|
||||
XCTAssertEqual(runTest(startACR: 0x40, endACR: 0xc0, portBOutput: 0xff), [0xff, 0xff, 0xff, 0x7f]) // ccca
|
||||
|
||||
// Third row.
|
||||
XCTAssertEqual(runTest(startACR: 0x80, endACR: 0x00, portBOutput: 0x00), [0x80, 0x00, 0x00, 0x00]) // b@@@ (i.e. 1, 0, 0, 0)
|
||||
XCTAssertEqual(runTest(startACR: 0x80, endACR: 0x40, portBOutput: 0x00), [0x80, 0x00, 0x00, 0x00]) // b@@@ (i.e. 1, 0, 0, 0)
|
||||
XCTAssertEqual(runTest(startACR: 0x80, endACR: 0x80, portBOutput: 0x00), [0x80, 0x00, 0x00, 0x80]) // b@@b (i.e. 1, 0, 0, 1)
|
||||
XCTAssertEqual(runTest(startACR: 0x80, endACR: 0xc0, portBOutput: 0x00), [0x80, 0x00, 0x00, 0x80]) // b@@b (i.e. 1, 0, 0, 1)
|
||||
|
||||
XCTAssertEqual(runTest(startACR: 0x80, endACR: 0x00, portBOutput: 0xff), [0xff, 0x7f, 0xff, 0xff]) // cacc (i.e. 1, 0, 1, 1)
|
||||
XCTAssertEqual(runTest(startACR: 0x80, endACR: 0x40, portBOutput: 0xff), [0xff, 0x7f, 0xff, 0xff]) // cacc (i.e. 1, 0, 1, 1)
|
||||
XCTAssertEqual(runTest(startACR: 0x80, endACR: 0x80, portBOutput: 0xff), [0xff, 0x7f, 0x7f, 0xff]) // caac (i.e. 1, 0, 0, 1)
|
||||
XCTAssertEqual(runTest(startACR: 0x80, endACR: 0xc0, portBOutput: 0xff), [0xff, 0x7f, 0x7f, 0xff]) // caac (i.e. 1, 0, 0, 1)
|
||||
|
||||
// Final row. [same output as third row]
|
||||
XCTAssertEqual(runTest(startACR: 0xc0, endACR: 0x00, portBOutput: 0x00), [0x80, 0x00, 0x00, 0x00]) // b@@@
|
||||
XCTAssertEqual(runTest(startACR: 0xc0, endACR: 0x40, portBOutput: 0x00), [0x80, 0x00, 0x00, 0x00]) // b@@@
|
||||
XCTAssertEqual(runTest(startACR: 0xc0, endACR: 0x80, portBOutput: 0x00), [0x80, 0x00, 0x00, 0x80]) // b@@b
|
||||
XCTAssertEqual(runTest(startACR: 0xc0, endACR: 0xc0, portBOutput: 0x00), [0x80, 0x00, 0x00, 0x80]) // b@@b
|
||||
|
||||
XCTAssertEqual(runTest(startACR: 0xc0, endACR: 0x00, portBOutput: 0xff), [0xff, 0x7f, 0xff, 0xff]) // cacc
|
||||
XCTAssertEqual(runTest(startACR: 0xc0, endACR: 0x40, portBOutput: 0xff), [0xff, 0x7f, 0xff, 0xff]) // cacc
|
||||
XCTAssertEqual(runTest(startACR: 0xc0, endACR: 0x80, portBOutput: 0xff), [0xff, 0x7f, 0x7f, 0xff]) // caac
|
||||
XCTAssertEqual(runTest(startACR: 0xc0, endACR: 0xc0, portBOutput: 0xff), [0xff, 0x7f, 0x7f, 0xff]) // caac
|
||||
|
||||
// Conclusions:
|
||||
//
|
||||
// after inital ACR and port B value: [original data if not in PB7 output mode, otherwise 1]
|
||||
// after starting timer 1: [original data if not in PB7 output mode, otherwise 0]
|
||||
// after final ACR value: [original data if not in PB7 output mode, 1 if has transitioned to PB7 mode, 0 if was already in PB7 mode]
|
||||
// after timer 1 expiry: [original data if not in PB7 mode, 1 if timer has expired while in PB7 mode]
|
||||
//
|
||||
// i.e.
|
||||
// (1) there is separate storage for the programmer-set PB7 and the timer output;
|
||||
// (2) the timer output is reset upon a timer write only if PB7 output is enabled;
|
||||
// (3) expiry toggles the output.
|
||||
}
|
||||
|
||||
|
||||
// MARK: Data direction tests
|
||||
func testDataDirection() {
|
||||
// set low four bits of register B as output, the top four as input
|
||||
|
||||
@ -70,12 +70,9 @@
|
||||
|
||||
- (void)testSeekToSecondBit {
|
||||
Storage::Disk::PCMSegmentEventSource segmentSource = self.segmentSource;
|
||||
Storage::Time target_time(1, 10);
|
||||
|
||||
Storage::Time found_time = segmentSource.seek_to(target_time);
|
||||
found_time.simplify();
|
||||
|
||||
XCTAssertTrue(found_time.length == 1 && found_time.clock_rate == 20, @"A request to seek to 1/10th should have seeked to 1/20th");
|
||||
const float found_time = segmentSource.seek_to(1.0f / 10.0f);
|
||||
XCTAssertTrue(fabsf(found_time - 1.0f / 20.0f) < 0.01f, @"A request to seek to 1/10th should have seeked to 1/20th");
|
||||
|
||||
Storage::Disk::Track::Event next_event = segmentSource.get_next_event();
|
||||
next_event.length.simplify();
|
||||
@ -85,12 +82,9 @@
|
||||
|
||||
- (void)testSeekBeyondFinalBit {
|
||||
Storage::Disk::PCMSegmentEventSource segmentSource = self.segmentSource;
|
||||
Storage::Time target_time(24, 10);
|
||||
const float found_time = segmentSource.seek_to(2.4f);
|
||||
|
||||
Storage::Time found_time = segmentSource.seek_to(target_time);
|
||||
found_time.simplify();
|
||||
|
||||
XCTAssertTrue(found_time.length == 47 && found_time.clock_rate == 20, @"A request to seek to 24/10ths should have seeked to 47/20ths");
|
||||
XCTAssertTrue(fabsf(found_time - 47.0f / 20.0f) < 0.01f, @"A request to seek to 24/10ths should have seeked to 47/20ths");
|
||||
|
||||
Storage::Disk::Track::Event next_event = segmentSource.get_next_event();
|
||||
next_event.length.simplify();
|
||||
|
||||
@ -73,16 +73,14 @@
|
||||
}
|
||||
|
||||
Storage::Disk::PCMTrack track(segments);
|
||||
Storage::Time late_time(967445, 2045454);
|
||||
const float late_time = 967445.0f / 2045454.0f;
|
||||
const auto offset = track.seek_to(late_time);
|
||||
XCTAssert(offset <= late_time, "Found location should be at or before sought time");
|
||||
|
||||
const auto difference = late_time - offset;
|
||||
const double difference_duration = difference.get<double>();
|
||||
XCTAssert(difference_duration >= 0.0 && difference_duration < 0.005, "Next event should occur soon");
|
||||
XCTAssert(difference >= 0.0 && difference < 0.005, "Next event should occur soon");
|
||||
|
||||
const double offset_duration = offset.get<double>();
|
||||
XCTAssert(offset_duration >= 0.0 && offset_duration < 0.5, "Next event should occur soon");
|
||||
XCTAssert(offset >= 0.0 && offset < 0.5, "Next event should occur soon");
|
||||
|
||||
auto next_event = track.get_next_event();
|
||||
double next_event_duration = next_event.length.get<double>();
|
||||
|
||||
Loading…
Reference in New Issue
Block a user