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https://github.com/TomHarte/CLK.git
synced 2025-01-12 15:31:09 +00:00
Prepare for additional devices.
This commit is contained in:
Thomas Harte
parent
5d6bb11eb7
commit
2ed031e440
@ -164,11 +164,31 @@ namespace IRQA {
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static constexpr uint8_t SetAlways = 0x80;
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}
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namespace InterruptRequests {
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// IRQ B flags
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namespace IRQB {
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// These are taken from the A3010 documentation.
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static constexpr uint8_t PoduleFIQRequest = 0x01;
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static constexpr uint8_t SoundBufferPointerUsed = 0x02;
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static constexpr uint8_t SerialLine = 0x04;
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static constexpr uint8_t IDE = 0x08;
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static constexpr uint8_t FloppyDiscInterrupt = 0x10;
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static constexpr uint8_t PoduleIRQRequest = 0x20;
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static constexpr uint8_t KeyboardTransmitEmpty = 0x40;
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static constexpr uint8_t KeyboardReceiveFull = 0x80;
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}
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// FIQ flags
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namespace FIQ {
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// These are taken from the A3010 documentation.
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static constexpr uint8_t FloppyDiscData = 0x01;
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static constexpr uint8_t SerialLine = 0x10;
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static constexpr uint8_t PoduleFIQRequest = 0x40;
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static constexpr uint8_t SetAlways = 0x80;
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}
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namespace InterruptRequests {
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static constexpr int IRQ = 0x01;
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static constexpr int FIQ = 0x02;
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};
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struct Interrupts {
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@ -203,38 +223,82 @@ struct Interrupts {
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return did_change_interrupts;
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}
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bool read(uint32_t address, uint8_t &value) const {
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const auto target = address & 0x7f;
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logger.error().append("IO controller read from %08x", address);
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switch(target) {
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default: break;
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static constexpr uint32_t AddressMask = 0x1f'ffff;
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case 0x00:
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bool read(uint32_t address, uint8_t &value) const {
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const auto target = address & AddressMask;
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switch(target) {
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default:
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logger.error().append("Unrecognised IOC read from %08x", address);
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break;
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case 0x3200000 & AddressMask:
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logger.error().append("TODO: IOC control read");
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value = 0;
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return true;
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case 0x3200004 & AddressMask:
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logger.error().append("TODO: IOC serial receive");
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value = 0;
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return true;
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// IRQ A.
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case 0x10: value = irq_a_.status; return true;
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case 0x14: value = irq_a_.request(); return true;
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case 0x18: value = irq_a_.mask; return true;
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case 0x3200010 & AddressMask:
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value = irq_a_.status;
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logger.error().append("IRQ A status is %02x", value);
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return true;
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case 0x3200014 & AddressMask:
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value = irq_a_.request();
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logger.error().append("IRQ A request is %02x", value);
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return true;
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case 0x3200018 & AddressMask:
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value = irq_a_.mask;
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logger.error().append("IRQ A mask is %02x", value);
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return true;
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// IRQ B.
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case 0x20: value = irq_b_.status; return true;
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case 0x24: value = irq_b_.request(); return true;
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case 0x28: value = irq_b_.mask; return true;
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case 0x3200020 & AddressMask:
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value = irq_b_.status;
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logger.error().append("IRQ B status is %02x", value);
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return true;
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case 0x3200024 & AddressMask:
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value = irq_b_.request();
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logger.error().append("IRQ B request is %02x", value);
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return true;
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case 0x3200028 & AddressMask:
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value = irq_b_.mask;
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logger.error().append("IRQ B mask is %02x", value);
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return true;
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// FIQ.
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case 0x30: value = fiq_.status; return true;
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case 0x34: value = fiq_.request(); return true;
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case 0x38: value = fiq_.mask; return true;
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case 0x3200030 & AddressMask:
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value = fiq_.status;
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logger.error().append("FIQ status is %02x", value);
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return true;
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case 0x3200034 & AddressMask:
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value = fiq_.request();
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logger.error().append("FIQ request is %02x", value);
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return true;
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case 0x3200038 & AddressMask:
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value = fiq_.mask;
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logger.error().append("FIQ mask is %02x", value);
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return true;
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// Counters.
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case 0x40: case 0x50: case 0x60: case 0x70:
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case 0x3200040 & AddressMask:
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case 0x3200050 & AddressMask:
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case 0x3200060 & AddressMask:
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case 0x3200070 & AddressMask:
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value = counters_[(target >> 4) - 0x4].output & 0xff;
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logger.error().append("%02x: Counter %d low is %02x", target, (target >> 4) - 0x4, value);
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return true;
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case 0x44: case 0x54: case 0x64: case 0x74:
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case 0x3200044 & AddressMask:
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case 0x3200054 & AddressMask:
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case 0x3200064 & AddressMask:
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case 0x3200074 & AddressMask:
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value = counters_[(target >> 4) - 0x4].output >> 8;
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logger.error().append("%02x: Counter %d high is %02x", target, (target >> 4) - 0x4, value);
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return true;
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}
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@ -242,16 +306,22 @@ struct Interrupts {
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}
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bool write(uint32_t address, uint8_t value) {
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const auto target = address & 0x7f;
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const auto target = address & AddressMask;
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logger.error().append("IO controller write of %02x at %08x", value, address);
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switch(target) {
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default: break;
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default:
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logger.error().append("Unrecognised IOC write of %02x at %08x", value, address);
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break;
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case 0x00:
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case 0x3200000 & AddressMask:
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logger.error().append("TODO: IOC control write %02x", value);
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return true;
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case 0x14:
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case 0x3200004 & AddressMask:
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logger.error().append("TODO: IOC serial transmit");
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return true;
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case 0x3200014 & AddressMask:
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// b2: clear IF.
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// b3: clear IR.
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// b4: clear POR.
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@ -261,26 +331,40 @@ struct Interrupts {
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return true;
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// Interrupts.
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case 0x18: irq_a_.mask = value; return true;
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case 0x28: irq_b_.mask = value; return true;
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case 0x38: fiq_.mask = value; return true;
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case 0x3200018 & AddressMask: irq_a_.mask = value; return true;
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case 0x3200028 & AddressMask: irq_b_.mask = value; return true;
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case 0x3200038 & AddressMask: fiq_.mask = value; return true;
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// Counters.
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case 0x40: case 0x50: case 0x60: case 0x70:
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case 0x3200040 & AddressMask:
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case 0x3200050 & AddressMask:
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case 0x3200060 & AddressMask:
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case 0x3200070 & AddressMask:
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counters_[(target >> 4) - 0x4].reload = uint16_t(
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(counters_[(target >> 4) - 0x4].reload & 0xff00) | value
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);
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return true;
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case 0x44: case 0x54: case 0x64: case 0x74:
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case 0x3200044 & AddressMask:
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case 0x3200054 & AddressMask:
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case 0x3200064 & AddressMask:
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case 0x3200074 & AddressMask:
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counters_[(target >> 4) - 0x4].reload = uint16_t(
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(counters_[(target >> 4) - 0x4].reload & 0x00ff) | (value << 8)
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);
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return true;
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case 0x48: case 0x58: case 0x68: case 0x78:
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case 0x3200048 & AddressMask:
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case 0x3200058 & AddressMask:
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case 0x3200068 & AddressMask:
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case 0x3200078 & AddressMask:
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counters_[(target >> 4) - 0x4].value = counters_[(target >> 4) - 0x4].reload;
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return true;
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case 0x4c: case 0x5c: case 0x6c: case 0x7c:
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case 0x320004c & AddressMask:
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case 0x320005c & AddressMask:
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case 0x320006c & AddressMask:
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case 0x320007c & AddressMask:
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counters_[(target >> 4) - 0x4].output = counters_[(target >> 4) - 0x4].value;
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return true;
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}
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@ -396,12 +480,13 @@ struct Memory {
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return true;
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case Zone::AddressTranslator:
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// printf("Translator write at %08x\n", address);
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pages_[address & 0x7f] = address;
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update_mapping();
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break;
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default:
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printf("TODO: write of %08x to %08x [%lu]\n", source, address, sizeof(IntT));
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// printf("TODO: write of %08x to %08x [%lu]\n", source, address, sizeof(IntT));
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break;
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}
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@ -457,9 +542,6 @@ struct Memory {
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// TODO: generalise this adaptation of an 8-bit device to the 32-bit bus, which probably isn't right anyway.
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uint8_t value;
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ioc_.read(address, value);
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// if(!ioc_.read(address, value)) {
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// return false;
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// }
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source = value;
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return true;
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}
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@ -606,6 +688,12 @@ struct Memory {
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}
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void update_mapping() {
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// static int c = 0;
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// ++c;
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// if(c == 662) {
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// printf("");
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// }
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// For each physical page, project it into logical space.
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switch(page_size_) {
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default:
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@ -615,7 +703,7 @@ struct Memory {
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case PageSize::kb32: update_mapping<PageSize::kb32>(); break;
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}
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logger.info().append("Updated logical RAM mapping");
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// logger.info().append("Updated logical RAM mapping [%d]", c);
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}
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template <PageSize size>
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@ -687,6 +775,8 @@ struct Memory {
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break;
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}
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// printf("%08x => logical %d -> physical %d\n", page, logical, (physical >> 15));
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// TODO: consider clashes.
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// TODO: what if there's less than 4mb present?
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mapping_[logical].target = &ram_[physical];
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