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Merge pull request #1090 from TomHarte/68000Tests
Add 68000 regression test generator.
This commit is contained in:
Thomas Harte
GitHub
commit
2edbbfbe37
@ -56,233 +56,209 @@ std::string Preinstruction::operand_description(int index, int opcode) const {
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}
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}
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std::string Preinstruction::to_string(int opcode) const {
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bool flip_operands = false;
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const char *instruction;
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namespace {
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const char *_to_string(Operation operation, bool is_quick) {
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switch(operation) {
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case Operation::Undefined: return "None";
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case Operation::NOP: instruction = "NOP"; break;
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case Operation::ABCD: instruction = "ABCD"; break;
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case Operation::SBCD: instruction = "SBCD"; break;
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case Operation::NBCD: instruction = "NBCD"; break;
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case Operation::Undefined: return "None";
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case Operation::NOP: return "NOP";
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case Operation::ABCD: return "ABCD";
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case Operation::SBCD: return "SBCD";
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case Operation::NBCD: return "NBCD";
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case Operation::ADDb: instruction = "ADD.b"; break;
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case Operation::ADDw: instruction = "ADD.w"; break;
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case Operation::ADDl: instruction = "ADD.l"; break;
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case Operation::ADDb: return "ADD.b";
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case Operation::ADDw: return "ADD.w";
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case Operation::ADDl: return "ADD.l";
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case Operation::ADDAw:
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if(mode<0>() == AddressingMode::Quick) {
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instruction = "ADD.w";
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} else {
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instruction = "ADDA.w";
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}
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break;
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case Operation::ADDAl:
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if(mode<0>() == AddressingMode::Quick) {
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instruction = "ADD.l";
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} else {
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instruction = "ADDA.l";
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}
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break;
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case Operation::ADDAw: return is_quick ? "ADD.w" : "ADDA.w";
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case Operation::ADDAl: return is_quick ? "ADD.l" : "ADDA.l";
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case Operation::ADDXb: instruction = "ADDX.b"; break;
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case Operation::ADDXw: instruction = "ADDX.w"; break;
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case Operation::ADDXl: instruction = "ADDX.l"; break;
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case Operation::ADDXb: return "ADDX.b";
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case Operation::ADDXw: return "ADDX.w";
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case Operation::ADDXl: return "ADDX.l";
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case Operation::SUBb: instruction = "SUB.b"; break;
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case Operation::SUBw: instruction = "SUB.w"; break;
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case Operation::SUBl: instruction = "SUB.l"; break;
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case Operation::SUBb: return "SUB.b";
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case Operation::SUBw: return "SUB.w";
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case Operation::SUBl: return "SUB.l";
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case Operation::SUBAw:
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if(mode<0>() == AddressingMode::Quick) {
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instruction = "SUB.w";
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} else {
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instruction = "SUBA.w";
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}
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break;
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case Operation::SUBAl:
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if(mode<0>() == AddressingMode::Quick) {
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instruction = "SUB.l";
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} else {
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instruction = "SUBA.l";
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}
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break;
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case Operation::SUBAw: return is_quick ? "SUB.w" : "SUBA.w";
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case Operation::SUBAl: return is_quick ? "SUB.l" : "SUBA.l";
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case Operation::SUBXb: instruction = "SUBX.b"; break;
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case Operation::SUBXw: instruction = "SUBX.w"; break;
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case Operation::SUBXl: instruction = "SUBX.l"; break;
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case Operation::SUBXb: return "SUBX.b";
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case Operation::SUBXw: return "SUBX.w";
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case Operation::SUBXl: return "SUBX.l";
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case Operation::MOVEb: instruction = "MOVE.b"; break;
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case Operation::MOVEw: instruction = "MOVE.w"; break;
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case Operation::MOVEl:
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if(mode<0>() == AddressingMode::Quick) {
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instruction = "MOVE.q";
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} else {
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instruction = "MOVE.l";
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}
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break;
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case Operation::MOVEb: return "MOVE.b";
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case Operation::MOVEw: return "MOVE.w";
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case Operation::MOVEl: return is_quick ? "MOVE.q" : "MOVE.l";
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case Operation::MOVEAw: instruction = "MOVEA.w"; break;
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case Operation::MOVEAl: instruction = "MOVEA.l"; break;
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case Operation::MOVEAw: return "MOVEA.w";
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case Operation::MOVEAl: return "MOVEA.l";
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case Operation::LEA: instruction = "LEA"; break;
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case Operation::PEA: instruction = "PEA"; break;
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case Operation::LEA: return "LEA";
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case Operation::PEA: return "PEA";
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case Operation::MOVEtoSR: instruction = "MOVEtoSR"; break;
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case Operation::MOVEfromSR: instruction = "MOVEfromSR"; break;
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case Operation::MOVEtoCCR: instruction = "MOVEtoCCR"; break;
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case Operation::MOVEtoUSP: instruction = "MOVEtoUSP"; break;
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case Operation::MOVEfromUSP: instruction = "MOVEfromUSP"; break;
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case Operation::MOVEtoSR: return "MOVEtoSR";
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case Operation::MOVEfromSR: return "MOVEfromSR";
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case Operation::MOVEtoCCR: return "MOVEtoCCR";
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case Operation::MOVEtoUSP: return "MOVEtoUSP";
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case Operation::MOVEfromUSP: return "MOVEfromUSP";
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case Operation::ORItoSR: instruction = "ORItoSR"; break;
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case Operation::ORItoCCR: instruction = "ORItoCCR"; break;
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case Operation::ANDItoSR: instruction = "ANDItoSR"; break;
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case Operation::ANDItoCCR: instruction = "ANDItoCCR"; break;
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case Operation::EORItoSR: instruction = "EORItoSR"; break;
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case Operation::EORItoCCR: instruction = "EORItoCCR"; break;
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case Operation::ORItoSR: return "ORItoSR";
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case Operation::ORItoCCR: return "ORItoCCR";
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case Operation::ANDItoSR: return "ANDItoSR";
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case Operation::ANDItoCCR: return "ANDItoCCR";
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case Operation::EORItoSR: return "EORItoSR";
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case Operation::EORItoCCR: return "EORItoCCR";
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case Operation::BTST: instruction = "BTST"; break;
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case Operation::BCLR: instruction = "BCLR"; break;
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case Operation::BCHG: instruction = "BCHG"; break;
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case Operation::BSET: instruction = "BSET"; break;
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case Operation::BTST: return "BTST";
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case Operation::BCLR: return "BCLR";
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case Operation::BCHG: return "BCHG";
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case Operation::BSET: return "BSET";
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case Operation::CMPb: instruction = "CMP.b"; break;
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case Operation::CMPw: instruction = "CMP.w"; break;
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case Operation::CMPl: instruction = "CMP.l"; break;
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case Operation::CMPb: return "CMP.b";
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case Operation::CMPw: return "CMP.w";
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case Operation::CMPl: return "CMP.l";
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case Operation::CMPAw: instruction = "CMPA.w"; break;
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case Operation::CMPAl: instruction = "CMPA.l"; break;
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case Operation::CMPAw: return "CMPA.w";
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case Operation::CMPAl: return "CMPA.l";
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case Operation::TSTb: instruction = "TST.b"; break;
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case Operation::TSTw: instruction = "TST.w"; break;
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case Operation::TSTl: instruction = "TST.l"; break;
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case Operation::TSTb: return "TST.b";
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case Operation::TSTw: return "TST.w";
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case Operation::TSTl: return "TST.l";
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case Operation::JMP: instruction = "JMP"; break;
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case Operation::JSR: instruction = "JSR"; break;
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case Operation::RTS: instruction = "RTS"; break;
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case Operation::DBcc: instruction = "DBcc"; break;
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case Operation::Scc: instruction = "Scc"; break;
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case Operation::JMP: return "JMP";
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case Operation::JSR: return "JSR";
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case Operation::RTS: return "RTS";
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case Operation::DBcc: return "DBcc";
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case Operation::Scc: return "Scc";
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case Operation::Bccb:
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case Operation::Bccl:
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case Operation::Bccw: instruction = "Bcc"; break;
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case Operation::Bccw: return "Bcc";
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case Operation::BSRb:
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case Operation::BSRl:
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case Operation::BSRw: instruction = "BSR"; break;
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case Operation::BSRw: return "BSR";
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case Operation::CLRb: instruction = "CLR.b"; break;
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case Operation::CLRw: instruction = "CLR.w"; break;
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case Operation::CLRl: instruction = "CLR.l"; break;
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case Operation::CLRb: return "CLR.b";
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case Operation::CLRw: return "CLR.w";
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case Operation::CLRl: return "CLR.l";
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case Operation::NEGXb: instruction = "NEGX.b"; break;
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case Operation::NEGXw: instruction = "NEGX.w"; break;
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case Operation::NEGXl: instruction = "NEGX.l"; break;
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case Operation::NEGXb: return "NEGX.b";
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case Operation::NEGXw: return "NEGX.w";
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case Operation::NEGXl: return "NEGX.l";
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case Operation::NEGb: instruction = "NEG.b"; break;
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case Operation::NEGw: instruction = "NEG.w"; break;
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case Operation::NEGl: instruction = "NEG.l"; break;
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case Operation::NEGb: return "NEG.b";
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case Operation::NEGw: return "NEG.w";
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case Operation::NEGl: return "NEG.l";
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case Operation::ASLb: instruction = "ASL.b"; break;
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case Operation::ASLw: instruction = "ASL.w"; break;
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case Operation::ASLl: instruction = "ASL.l"; break;
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case Operation::ASLm: instruction = "ASL.w"; break;
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case Operation::ASLb: return "ASL.b";
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case Operation::ASLw: return "ASL.w";
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case Operation::ASLl: return "ASL.l";
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case Operation::ASLm: return "ASL.w";
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case Operation::ASRb: instruction = "ASR.b"; break;
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case Operation::ASRw: instruction = "ASR.w"; break;
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case Operation::ASRl: instruction = "ASR.l"; break;
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case Operation::ASRm: instruction = "ASR.w"; break;
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case Operation::ASRb: return "ASR.b";
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case Operation::ASRw: return "ASR.w";
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case Operation::ASRl: return "ASR.l";
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case Operation::ASRm: return "ASR.w";
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case Operation::LSLb: instruction = "LSL.b"; break;
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case Operation::LSLw: instruction = "LSL.w"; break;
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case Operation::LSLl: instruction = "LSL.l"; break;
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case Operation::LSLm: instruction = "LSL.w"; break;
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case Operation::LSLb: return "LSL.b";
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case Operation::LSLw: return "LSL.w";
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case Operation::LSLl: return "LSL.l";
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case Operation::LSLm: return "LSL.w";
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case Operation::LSRb: instruction = "LSR.b"; break;
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case Operation::LSRw: instruction = "LSR.w"; break;
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case Operation::LSRl: instruction = "LSR.l"; break;
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case Operation::LSRm: instruction = "LSR.w"; break;
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case Operation::LSRb: return "LSR.b";
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case Operation::LSRw: return "LSR.w";
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case Operation::LSRl: return "LSR.l";
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case Operation::LSRm: return "LSR.w";
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case Operation::ROLb: instruction = "ROL.b"; break;
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case Operation::ROLw: instruction = "ROL.w"; break;
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case Operation::ROLl: instruction = "ROL.l"; break;
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case Operation::ROLm: instruction = "ROL.w"; break;
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case Operation::ROLb: return "ROL.b";
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case Operation::ROLw: return "ROL.w";
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case Operation::ROLl: return "ROL.l";
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case Operation::ROLm: return "ROL.w";
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case Operation::RORb: instruction = "ROR.b"; break;
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case Operation::RORw: instruction = "ROR.w"; break;
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case Operation::RORl: instruction = "ROR.l"; break;
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case Operation::RORm: instruction = "ROR.w"; break;
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case Operation::RORb: return "ROR.b";
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case Operation::RORw: return "ROR.w";
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case Operation::RORl: return "ROR.l";
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case Operation::RORm: return "ROR.w";
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case Operation::ROXLb: instruction = "ROXL.b"; break;
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case Operation::ROXLw: instruction = "ROXL.w"; break;
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case Operation::ROXLl: instruction = "ROXL.l"; break;
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case Operation::ROXLm: instruction = "ROXL.w"; break;
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case Operation::ROXLb: return "ROXL.b";
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case Operation::ROXLw: return "ROXL.w";
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case Operation::ROXLl: return "ROXL.l";
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case Operation::ROXLm: return "ROXL.w";
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case Operation::ROXRb: instruction = "ROXR.b"; break;
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case Operation::ROXRw: instruction = "ROXR.w"; break;
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case Operation::ROXRl: instruction = "ROXR.l"; break;
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case Operation::ROXRm: instruction = "ROXR.w"; break;
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case Operation::ROXRb: return "ROXR.b";
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case Operation::ROXRw: return "ROXR.w";
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case Operation::ROXRl: return "ROXR.l";
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case Operation::ROXRm: return "ROXR.w";
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case Operation::MOVEMtoMl: instruction = "MOVEM.l"; break;
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case Operation::MOVEMtoMw: instruction = "MOVEM.w"; break;
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case Operation::MOVEMtoRl:
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instruction = "MOVEM.l";
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flip_operands = true;
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break;
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case Operation::MOVEMtoRw:
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instruction = "MOVEM.w";
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flip_operands = true;
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break;
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case Operation::MOVEMtoMl: return "MOVEM.l";
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case Operation::MOVEMtoMw: return "MOVEM.w";
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case Operation::MOVEMtoRl: return "MOVEM.l";
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case Operation::MOVEMtoRw: return "MOVEM.w";
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case Operation::MOVEPl: instruction = "MOVEP.l"; break;
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case Operation::MOVEPw: instruction = "MOVEP.w"; break;
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case Operation::MOVEPl: return "MOVEP.l";
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case Operation::MOVEPw: return "MOVEP.w";
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case Operation::ANDb: instruction = "AND.b"; break;
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case Operation::ANDw: instruction = "AND.w"; break;
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case Operation::ANDl: instruction = "AND.l"; break;
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case Operation::ANDb: return "AND.b";
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case Operation::ANDw: return "AND.w";
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case Operation::ANDl: return "AND.l";
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case Operation::EORb: instruction = "EOR.b"; break;
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case Operation::EORw: instruction = "EOR.w"; break;
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case Operation::EORl: instruction = "EOR.l"; break;
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case Operation::EORb: return "EOR.b";
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case Operation::EORw: return "EOR.w";
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case Operation::EORl: return "EOR.l";
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case Operation::NOTb: instruction = "NOT.b"; break;
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case Operation::NOTw: instruction = "NOT.w"; break;
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case Operation::NOTl: instruction = "NOT.l"; break;
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case Operation::NOTb: return "NOT.b";
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case Operation::NOTw: return "NOT.w";
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case Operation::NOTl: return "NOT.l";
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case Operation::ORb: instruction = "OR.b"; break;
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case Operation::ORw: instruction = "OR.w"; break;
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case Operation::ORl: instruction = "OR.l"; break;
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case Operation::ORb: return "OR.b";
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case Operation::ORw: return "OR.w";
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case Operation::ORl: return "OR.l";
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case Operation::MULU: instruction = "MULU"; break;
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case Operation::MULS: instruction = "MULS"; break;
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case Operation::DIVU: instruction = "DIVU"; break;
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case Operation::DIVS: instruction = "DIVS"; break;
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case Operation::MULU: return "MULU";
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case Operation::MULS: return "MULS";
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case Operation::DIVU: return "DIVU";
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case Operation::DIVS: return "DIVS";
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case Operation::RTE: instruction = "RTE"; break;
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case Operation::RTR: instruction = "RTR"; break;
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case Operation::RTE: return "RTE";
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case Operation::RTR: return "RTR";
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case Operation::TRAP: instruction = "TRAP"; break;
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case Operation::TRAPV: instruction = "TRAPV"; break;
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case Operation::CHK: instruction = "CHK"; break;
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case Operation::TRAP: return "TRAP";
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case Operation::TRAPV: return "TRAPV";
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case Operation::CHK: return "CHK";
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case Operation::EXG: instruction = "EXG"; break;
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case Operation::SWAP: instruction = "SWAP"; break;
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case Operation::EXG: return "EXG";
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case Operation::SWAP: return "SWAP";
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case Operation::TAS: instruction = "TAS"; break;
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case Operation::TAS: return "TAS";
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case Operation::EXTbtow: instruction = "EXT.w"; break;
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case Operation::EXTwtol: instruction = "EXT.l"; break;
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case Operation::EXTbtow: return "EXT.w";
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case Operation::EXTwtol: return "EXT.l";
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case Operation::LINKw: instruction = "LINK"; break;
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case Operation::UNLINK: instruction = "UNLINK"; break;
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case Operation::LINKw: return "LINK";
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case Operation::UNLINK: return "UNLINK";
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case Operation::STOP: instruction = "STOP"; break;
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case Operation::RESET: instruction = "RESET"; break;
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case Operation::STOP: return "STOP";
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case Operation::RESET: return "RESET";
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default:
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assert(false);
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}
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}
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}
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const char *InstructionSet::M68k::to_string(Operation operation) {
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return _to_string(operation, false);
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}
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std::string Preinstruction::to_string(int opcode) const {
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if(operation == Operation::Undefined) return "None";
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const char *const instruction = _to_string(operation, mode<0>() == AddressingMode::Quick);
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const bool flip_operands = (operation == Operation::MOVEMtoRl) || (operation == Operation::MOVEMtoRw);
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const std::string operand1 = operand_description(0 ^ int(flip_operands), opcode);
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const std::string operand2 = operand_description(1 ^ int(flip_operands), opcode);
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@ -293,3 +269,7 @@ std::string Preinstruction::to_string(int opcode) const {
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return result;
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}
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const char *Preinstruction::operation_string() const {
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return _to_string(operation, mode<0>() == AddressingMode::Quick);
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}
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@ -104,6 +104,8 @@ enum class Operation: uint8_t {
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Max = RESET
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};
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const char *to_string(Operation op);
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template <Model model>
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constexpr bool requires_supervisor(Operation op) {
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switch(op) {
|
||||
@ -346,6 +348,12 @@ class Preinstruction {
|
||||
/// is supplied then any quick fields in this instruction will be decoded;
|
||||
/// otherwise they'll be printed as just 'Q'.
|
||||
std::string to_string(int opcode = -1) const;
|
||||
|
||||
/// Produces a slightly-more-idiomatic version of the operation name than
|
||||
/// a direct to_string(instruction.operation) would, given that this decoder
|
||||
/// sometimes aliases operations, disambiguating based on addressing mode
|
||||
/// (e.g. MOVEQ is MOVE.l with the Q addressing mode).
|
||||
const char *operation_string() const;
|
||||
};
|
||||
|
||||
}
|
||||
|
||||
@ -14,6 +14,7 @@
|
||||
|
||||
#include <array>
|
||||
#include <unordered_map>
|
||||
#include <unordered_set>
|
||||
#include <set>
|
||||
|
||||
namespace {
|
||||
@ -56,16 +57,18 @@ struct Transaction {
|
||||
uint32_t address = 0;
|
||||
uint16_t value = 0;
|
||||
bool address_strobe = false;
|
||||
bool same_address = false;
|
||||
bool read = false;
|
||||
int data_strobes = 0;
|
||||
|
||||
bool operator !=(const Transaction &rhs) const {
|
||||
bool operator != (const Transaction &rhs) const {
|
||||
if(timestamp != rhs.timestamp) return true;
|
||||
// if(function_code != rhs.function_code) return true;
|
||||
if(address != rhs.address) return true;
|
||||
if(value != rhs.value) return true;
|
||||
if(address_strobe != rhs.address_strobe) return true;
|
||||
if(data_strobes != rhs.data_strobes) return true;
|
||||
if(same_address != rhs.same_address) return true;
|
||||
return false;
|
||||
}
|
||||
|
||||
@ -108,6 +111,7 @@ struct BusHandler {
|
||||
transaction.function_code |= (cycle.operation & Microcycle::IsData) ? 0x1 : 0x2;
|
||||
}
|
||||
transaction.address_strobe = cycle.operation & (Microcycle::NewAddress | Microcycle::SameAddress);
|
||||
transaction.same_address = cycle.operation & Microcycle::SameAddress;
|
||||
transaction.data_strobes = cycle.operation & (Microcycle::SelectByte | Microcycle::SelectWord);
|
||||
if(cycle.address) transaction.address = *cycle.address & 0xffff'ff;
|
||||
transaction.timestamp = time;
|
||||
@ -116,7 +120,7 @@ struct BusHandler {
|
||||
time += cycle.length;
|
||||
|
||||
// Do the operation...
|
||||
const uint32_t address = cycle.address ? (*cycle.address & 0xffff'ff) : 0;
|
||||
const uint32_t address = cycle.address ? (*cycle.address & 0xff'ffff) : 0;
|
||||
switch(cycle.operation & (Microcycle::SelectWord | Microcycle::SelectByte | Microcycle::Read)) {
|
||||
default: break;
|
||||
|
||||
@ -153,14 +157,13 @@ struct BusHandler {
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
// Add the data value if relevant.
|
||||
if(transaction.data_strobes) {
|
||||
transaction.value = cycle.value16();
|
||||
}
|
||||
|
||||
// Push back only if interesting.
|
||||
if(transaction.address_strobe || transaction.data_strobes || transaction.function_code == 7) {
|
||||
if(capture_all_transactions || transaction.address_strobe || transaction.data_strobes || transaction.function_code == 7) {
|
||||
if(transaction_delay) {
|
||||
--transaction_delay;
|
||||
|
||||
@ -178,6 +181,7 @@ struct BusHandler {
|
||||
|
||||
int transaction_delay;
|
||||
int instructions;
|
||||
bool capture_all_transactions = false;
|
||||
|
||||
HalfCycles time;
|
||||
std::vector<Transaction> transactions;
|
||||
@ -238,6 +242,150 @@ template <typename M68000> struct Tester {
|
||||
M68000 processor;
|
||||
};
|
||||
|
||||
void print_state(FILE *target, const CPU::MC68000Mk2::State &state, const std::vector<Transaction> &transactions, bool is_initial) {
|
||||
for(int c = 0; c < 8; c++) {
|
||||
fprintf(target, "\"d%d\": %u, ", c, state.registers.data[c]);
|
||||
}
|
||||
|
||||
for(int c = 0; c < 7; c++) {
|
||||
fprintf(target, "\"a%d\": %u, ", c, state.registers.address[c]);
|
||||
}
|
||||
|
||||
fprintf(target, "\"usp\": %u, ", state.registers.user_stack_pointer);
|
||||
fprintf(target, "\"ssp\": %u, ", state.registers.supervisor_stack_pointer);
|
||||
fprintf(target, "\"sr\": %u, ", state.registers.status);
|
||||
fprintf(target, "\"pc\": %u, ", state.registers.program_counter - 4);
|
||||
|
||||
fprintf(target, "\"prefetch\": [%u, %u], ", state.prefetch[0], state.prefetch[1]);
|
||||
|
||||
fprintf(target, "\"ram\": [");
|
||||
|
||||
// Compute RAM from transactions; if this is the initial state then RAM should
|
||||
// be everything that was subject to a read which had not previously been
|
||||
// subject to a write. Otherwise it can just be everything.
|
||||
std::unordered_map<uint32_t, uint8_t> ram;
|
||||
if(is_initial) {
|
||||
std::unordered_set<uint32_t> written_addresses;
|
||||
|
||||
for(const auto &transaction: transactions) {
|
||||
switch(transaction.data_strobes) {
|
||||
default: continue;
|
||||
case 1:
|
||||
if(transaction.read) {
|
||||
if(ram.find(transaction.address) == ram.end()) {
|
||||
ram[transaction.address] = transaction.value;
|
||||
}
|
||||
} else {
|
||||
written_addresses.insert(transaction.address);
|
||||
}
|
||||
break;
|
||||
case 2:
|
||||
if(transaction.read) {
|
||||
if(ram.find(transaction.address) == ram.end()) {
|
||||
ram[transaction.address] = uint8_t(transaction.value >> 8);
|
||||
}
|
||||
if(ram.find(transaction.address+1) == ram.end()) {
|
||||
ram[transaction.address+1] = uint8_t(transaction.value);
|
||||
}
|
||||
} else {
|
||||
written_addresses.insert(transaction.address);
|
||||
written_addresses.insert(transaction.address + 1);
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
for(const auto &transaction: transactions) {
|
||||
switch(transaction.data_strobes) {
|
||||
default: continue;
|
||||
case 1:
|
||||
ram[transaction.address] = transaction.value;
|
||||
break;
|
||||
case 2:
|
||||
ram[transaction.address] = uint8_t(transaction.value >> 8);
|
||||
ram[transaction.address+1] = uint8_t(transaction.value);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bool is_first = true;
|
||||
for(const auto &pair: ram) {
|
||||
if(!is_first) fprintf(target, ", ");
|
||||
is_first = false;
|
||||
fprintf(target, "[%d, %d]", pair.first, pair.second);
|
||||
}
|
||||
fprintf(target, "]");
|
||||
}
|
||||
|
||||
void print_transactions(FILE *target, const std::vector<Transaction> &transactions, HalfCycles end) {
|
||||
auto iterator = transactions.begin();
|
||||
bool is_first = true;
|
||||
do {
|
||||
if(!is_first) fprintf(target, ", ");
|
||||
is_first = false;
|
||||
fprintf(target, "[");
|
||||
|
||||
auto next = iterator + 1;
|
||||
|
||||
// Attempt to pair off transactions to reproduct YACHT notation.
|
||||
bool is_access = true;
|
||||
if(!iterator->address_strobe && !iterator->data_strobes) {
|
||||
fprintf(target, "\"n\", ");
|
||||
is_access = false;
|
||||
} else {
|
||||
assert(!iterator->data_strobes);
|
||||
|
||||
// Check how many transactions this address persists for;
|
||||
// that'll allow a TAS to be recognised here.
|
||||
while(next->same_address && next != transactions.end()) {
|
||||
++next;
|
||||
}
|
||||
--next;
|
||||
|
||||
if(next == iterator + 1) {
|
||||
if(next->read) {
|
||||
fprintf(target, "\"r\", ");
|
||||
} else {
|
||||
fprintf(target, "\"w\", ");
|
||||
}
|
||||
} else {
|
||||
fprintf(target, "\"t\", ");
|
||||
}
|
||||
|
||||
// Include next in the calculation of time below.
|
||||
++next;
|
||||
}
|
||||
HalfCycles length;
|
||||
if(next == transactions.end()) {
|
||||
length = end - iterator->timestamp;
|
||||
} else {
|
||||
length = next->timestamp - iterator->timestamp;
|
||||
}
|
||||
fprintf(target, "%d", length.as<int>() >> 1);
|
||||
|
||||
if(is_access) {
|
||||
// Undo the 'move to one after' step that allowed next to be included
|
||||
// in this transaction's cycle count.
|
||||
--next;
|
||||
|
||||
fprintf(target, ", %d, ", iterator->function_code);
|
||||
fprintf(target, "%d, ", iterator->address & 0xff'ffff);
|
||||
|
||||
switch(next->data_strobes) {
|
||||
default: assert(false);
|
||||
case 1: fprintf(target, "\".b\", %d", next->value & 0xff); break;
|
||||
case 2: fprintf(target, "\".w\", %d", next->value); break;
|
||||
}
|
||||
|
||||
++next;
|
||||
}
|
||||
|
||||
fprintf(target, "]");
|
||||
iterator = next;
|
||||
} while(iterator != transactions.end());
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
@interface M68000OldVsNewTests : XCTestCase
|
||||
@ -245,6 +393,120 @@ template <typename M68000> struct Tester {
|
||||
|
||||
@implementation M68000OldVsNewTests
|
||||
|
||||
//- (void)testGenerate {
|
||||
- (void)generate {
|
||||
srand(68000);
|
||||
InstructionSet::M68k::Predecoder<InstructionSet::M68k::Model::M68000> decoder;
|
||||
RandomStore random_store;
|
||||
auto tester = std::make_unique<Tester<NewProcessor>>(random_store, 0x02);
|
||||
tester->bus_handler.capture_all_transactions = true;
|
||||
|
||||
// Bucket opcodes by operation.
|
||||
std::unordered_map<const char *, std::vector<uint16_t>> opcodesByOperation;
|
||||
for(int c = 0; c < 65536; c++) {
|
||||
// Test only defined opcodes that aren't STOP (which will never teminate).
|
||||
const auto instruction = decoder.decode(uint16_t(c));
|
||||
if(
|
||||
instruction.operation == InstructionSet::M68k::Operation::Undefined ||
|
||||
instruction.operation == InstructionSet::M68k::Operation::STOP
|
||||
) {
|
||||
continue;
|
||||
}
|
||||
|
||||
const auto operation = instruction.operation_string();
|
||||
opcodesByOperation[operation].push_back(c);
|
||||
}
|
||||
|
||||
// Find somewhere to write to.
|
||||
NSString *const tempDir = NSTemporaryDirectory();
|
||||
NSLog(@"Outputting to %@", tempDir);
|
||||
|
||||
// Aim to get at least 1,000,000 tests total.
|
||||
const auto testsPerOperation = int((1'000'000 + (opcodesByOperation.size() - 1)) / opcodesByOperation.size());
|
||||
|
||||
// Generate by operation.
|
||||
NSLog(@"Generating %d tests each for %lu operations", testsPerOperation, opcodesByOperation.size());
|
||||
for(const auto &pair: opcodesByOperation) {
|
||||
NSLog(@"Generating %s", pair.first);
|
||||
NSString *const targetName = [NSString stringWithFormat:@"%@%s.json", tempDir, pair.first];
|
||||
FILE *const target = fopen(targetName.UTF8String, "wt");
|
||||
|
||||
const bool force_addresses_even = decoder.decode(pair.second[0]).operation == InstructionSet::M68k::Operation::UNLINK;
|
||||
bool is_first_test = true;
|
||||
fprintf(target, "[");
|
||||
|
||||
// Test each for the selected number of iterations.
|
||||
for(int test = 0; test < testsPerOperation; test++) {
|
||||
if(!is_first_test) fprintf(target, ",\n");
|
||||
is_first_test = false;
|
||||
|
||||
// Establish with certainty the initial memory state.
|
||||
random_store.clear();
|
||||
|
||||
const auto opcodeIndex = int(rand() * pair.second.size() / RAND_MAX);
|
||||
const uint16_t opcode = pair.second[opcodeIndex];
|
||||
tester->reset_with_opcode(opcode);
|
||||
|
||||
// Generate a random initial register state.
|
||||
auto initialState = tester->processor.get_state();
|
||||
|
||||
// Require address pointers to be even 99% of the time, or always for UNLINK.
|
||||
const bool addresses_are_even = (rand() >= int(float(RAND_MAX) * 0.99f)) || force_addresses_even;
|
||||
for(int c = 0; c < 8; c++) {
|
||||
initialState.registers.data[c] = rand() ^ (rand() << 1);
|
||||
if(c != 7) {
|
||||
initialState.registers.address[c] = rand() ^ (rand() << 1);
|
||||
if(addresses_are_even) initialState.registers.address[c] &= ~1;
|
||||
}
|
||||
}
|
||||
|
||||
// Pick a random status such that:
|
||||
//
|
||||
// (i) supervisor mode is active 99% of the time;
|
||||
// (ii) trace is inactive; and
|
||||
// (iii) interrupt level is 7.
|
||||
const bool is_supervisor = rand() >= int(float(RAND_MAX) * 0.99f);
|
||||
initialState.registers.status = (rand() | (int(is_supervisor) << 13) | (7 << 8)) & ~(1 << 15);
|
||||
initialState.registers.user_stack_pointer = rand() << 1;
|
||||
initialState.registers.supervisor_stack_pointer = rand() << 1;
|
||||
|
||||
// Set state.
|
||||
tester->processor.set_state(initialState);
|
||||
|
||||
// Run for zero instructions to grab the real initial state (i.e. valid prefetch, ssp, etc).
|
||||
// Then make sure no transactions or time carry over into the actual instruction.
|
||||
tester->run_instructions(0);
|
||||
auto populatedInitialState = tester->processor.get_state();
|
||||
tester->bus_handler.transactions.clear();
|
||||
tester->bus_handler.time = HalfCycles(0);
|
||||
|
||||
// Run for another instruction to do the actual work.
|
||||
tester->run_instructions(1);
|
||||
|
||||
const auto finalState = tester->processor.get_state();
|
||||
|
||||
// Output initial state.
|
||||
fprintf(target, "{ \"name\": \"%04x [%s] %d\", ", opcode, decoder.decode(opcode).to_string().c_str(), test + 1);
|
||||
fprintf(target, "\"initial\": {");
|
||||
print_state(target, populatedInitialState, tester->bus_handler.transactions, true);
|
||||
|
||||
// Output final state.
|
||||
fprintf(target, "}, \"final\": {");
|
||||
print_state(target, finalState, tester->bus_handler.transactions, false);
|
||||
|
||||
// Output total length and bus activity.
|
||||
fprintf(target, "}, \"length\": %d, ", tester->bus_handler.time.as<int>() >> 1);
|
||||
|
||||
fprintf(target, "\"transactions\": [");
|
||||
print_transactions(target, tester->bus_handler.transactions, tester->bus_handler.time);
|
||||
fprintf(target, "]}");
|
||||
}
|
||||
|
||||
fprintf(target, "\n]\n");
|
||||
fclose(target);
|
||||
}
|
||||
}
|
||||
|
||||
- (void)testOldVsNew {
|
||||
RandomStore random_store;
|
||||
auto oldTester = std::make_unique<Tester<OldProcessor>>(random_store, 0x01);
|
||||
@ -294,7 +556,7 @@ template <typename M68000> struct Tester {
|
||||
int testsRun = 0;
|
||||
std::set<InstructionSet::M68k::Operation> failing_operations;
|
||||
for(int c = 0; c < 65536; c++) {
|
||||
// printf("%04x\n", c);
|
||||
printf("%04x\n", c);
|
||||
|
||||
// Test only defined opcodes that aren't STOP (which will never teminate).
|
||||
const auto instruction = decoder.decode(uint16_t(c));
|
||||
|
||||
@ -354,6 +354,7 @@ class BusHandler {
|
||||
};
|
||||
|
||||
struct State {
|
||||
uint16_t prefetch[2];
|
||||
InstructionSet::M68k::RegisterSet registers;
|
||||
};
|
||||
|
||||
|
||||
@ -341,7 +341,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
|
||||
// Sets up the next data access size and read flags.
|
||||
#define SetupDataAccess(read_flag, select_flag) \
|
||||
access_announce.operation = Microcycle::NewAddress | Microcycle::IsData | (read_flag); \
|
||||
access.operation = access_announce.operation | (select_flag);
|
||||
access.operation = Microcycle::SameAddress | Microcycle::IsData | (read_flag) | (select_flag);
|
||||
|
||||
// Sets the address source for the next data access.
|
||||
#define SetDataAddress(addr) \
|
||||
@ -3025,6 +3025,9 @@ CPU::MC68000Mk2::State Processor<BusHandler, dtack_is_implicit, permit_overrun,
|
||||
state.registers.user_stack_pointer = stack_pointers_[0].l;
|
||||
state.registers.supervisor_stack_pointer = stack_pointers_[1].l;
|
||||
|
||||
state.prefetch[0] = prefetch_.high.w;
|
||||
state.prefetch[1] = prefetch_.low.w;
|
||||
|
||||
return state;
|
||||
}
|
||||
|
||||
@ -3048,6 +3051,10 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
|
||||
|
||||
// Ensure the local is-supervisor flag is updated.
|
||||
did_update_status();
|
||||
|
||||
// Populate the prefetch.
|
||||
prefetch_.high.w = state.prefetch[0];
|
||||
prefetch_.low.w = state.prefetch[1];
|
||||
}
|
||||
|
||||
template <class BusHandler, bool dtack_is_implicit, bool permit_overrun, bool signal_will_perform>
|
||||
|
||||
Loading…
Reference in New Issue
Block a user