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https://github.com/TomHarte/CLK.git
synced 2024-11-26 08:49:37 +00:00
Use null for values that were never loaded.
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parent
7dcfa9eb65
commit
2f684ee66d
@ -10,6 +10,7 @@
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#import <XCTest/XCTest.h>
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#import <XCTest/XCTest.h>
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#include <array>
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#include <array>
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#include <optional>
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#include <vector>
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#include <vector>
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#include <unordered_map>
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#include <unordered_map>
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@ -27,7 +28,6 @@ struct BusHandler: public CPU::MOS6502Esque::BusHandler<uint32_t> {
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auto &cycle = cycles.emplace_back();
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auto &cycle = cycles.emplace_back();
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cycle.address = address;
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cycle.address = address;
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cycle.operation = operation;
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cycle.operation = operation;
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cycle.value = 0xff;
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cycle.extended_bus = processor.get_extended_bus_output();
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cycle.extended_bus = processor.get_extended_bus_output();
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// Perform the operation, and fill in the cycle's value.
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// Perform the operation, and fill in the cycle's value.
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@ -47,7 +47,7 @@ struct BusHandler: public CPU::MOS6502Esque::BusHandler<uint32_t> {
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cycle.value = *value = ram_value->second;
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cycle.value = *value = ram_value->second;
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} else {
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} else {
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cycle.value = *value = uint8_t(rand() >> 8);
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cycle.value = *value = uint8_t(rand() >> 8);
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inventions[address] = ram[address] = cycle.value;
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inventions[address] = ram[address] = *cycle.value;
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}
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}
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break;
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break;
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@ -79,7 +79,7 @@ struct BusHandler: public CPU::MOS6502Esque::BusHandler<uint32_t> {
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struct Cycle {
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struct Cycle {
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CPU::MOS6502Esque::BusOperation operation;
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CPU::MOS6502Esque::BusOperation operation;
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uint32_t address;
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uint32_t address;
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uint8_t value;
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std::optional<uint8_t> value;
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int extended_bus;
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int extended_bus;
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};
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};
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std::vector<Cycle> cycles;
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std::vector<Cycle> cycles;
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@ -229,9 +229,13 @@ void print_ram(FILE *file, const std::unordered_map<uint32_t, uint8_t> &data) {
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const bool index_size = cycle.extended_bus & ExtendedBusOutput::IndexSize;
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const bool index_size = cycle.extended_bus & ExtendedBusOutput::IndexSize;
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const bool memory_lock = cycle.extended_bus & ExtendedBusOutput::MemoryLock;
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const bool memory_lock = cycle.extended_bus & ExtendedBusOutput::MemoryLock;
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fprintf(target, "[%d, %d, \"%c%c%c%c%c%c%c%c\"]",
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fprintf(target, "[%d, ", cycle.address);
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cycle.address,
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if(cycle.value) {
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cycle.value,
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fprintf(target, "%d, ", *cycle.value);
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} else {
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fprintf(target, "null, ");
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}
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fprintf(target, "\"%c%c%c%c%c%c%c%c\"]",
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vda ? 'd' : '-',
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vda ? 'd' : '-',
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vpa ? 'p' : '-',
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vpa ? 'p' : '-',
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vpb ? 'v' : '-',
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vpb ? 'v' : '-',
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