From 2f7f11e2e59226429a32a418bba3ca5dad5d0e82 Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Wed, 31 May 2017 06:54:25 -0400
Subject: [PATCH] Added diagnosis props.

---
 OSBindings/Mac/Clock SignalTests/FUSETests.swift | 7 ++++---
 Processors/Z80/Z80AllRAM.cpp                     | 3 +++
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/OSBindings/Mac/Clock SignalTests/FUSETests.swift b/OSBindings/Mac/Clock SignalTests/FUSETests.swift
index f33d09487..8409d95ac 100644
--- a/OSBindings/Mac/Clock SignalTests/FUSETests.swift	
+++ b/OSBindings/Mac/Clock SignalTests/FUSETests.swift	
@@ -167,9 +167,10 @@ class FUSETests: XCTestCase {
 
 			let name = itemDictionary["name"] as! String
 
-			if name != "02" {
-				continue;
-			}
+//			if name != "02" {
+//				continue;
+//			}
+			print("\(name)")
 
 			let initialState = RegisterState(dictionary: itemDictionary["state"] as! [String: Any])
 			let targetState = RegisterState(dictionary: outputDictionary["state"] as! [String: Any])
diff --git a/Processors/Z80/Z80AllRAM.cpp b/Processors/Z80/Z80AllRAM.cpp
index cec8c07ae..d1a3c61eb 100644
--- a/Processors/Z80/Z80AllRAM.cpp
+++ b/Processors/Z80/Z80AllRAM.cpp
@@ -20,11 +20,14 @@ class ConcreteAllRAMProcessor: public AllRAMProcessor, public Processor<Concrete
 			uint16_t address = cycle.address ? *cycle.address : 0x0000;
 			switch(cycle.operation) {
 				case BusOperation::ReadOpcode:
+					printf("! ");
 					check_address_for_trap(address);
 				case BusOperation::Read:
+					printf("r %04x [%02x] AF:%04x BC:%04x DE:%04x HL:%04x SP:%04x\n", address, memory_[address], get_value_of_register(CPU::Z80::Register::AF), get_value_of_register(CPU::Z80::Register::BC), get_value_of_register(CPU::Z80::Register::DE), get_value_of_register(CPU::Z80::Register::HL), get_value_of_register(CPU::Z80::Register::StackPointer));
 					*cycle.value = memory_[address];
 				break;
 				case BusOperation::Write:
+					printf("w %04x\n", address);
 					memory_[address] = *cycle.value;
 				break;