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https://github.com/TomHarte/CLK.git
synced 2024-12-25 18:30:21 +00:00
Merge pull request #987 from TomHarte/IIgsImprovements
Further iterates the IIgs towards full functionality.
This commit is contained in:
commit
2f86dfdf2b
@ -29,7 +29,7 @@ struct Target: public Analyser::Static::Target, public Reflection::StructImpl<Ta
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EightMB
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);
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Model model = Model::ROM03;
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Model model = Model::ROM01;
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MemoryModel memory_model = MemoryModel::EightMB;
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Target() : Analyser::Static::Target(Machine::AppleIIgs) {
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@ -9,6 +9,8 @@
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#ifndef Apple_RealTimeClock_hpp
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#define Apple_RealTimeClock_hpp
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#include <array>
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namespace Apple {
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namespace Clock {
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@ -21,32 +23,36 @@ namespace Clock {
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*/
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class ClockStorage {
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public:
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ClockStorage() {
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// TODO: this should persist, if possible, rather than
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// being default initialised.
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constexpr uint8_t default_data[] = {
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0xa8, 0x00, 0x00, 0x00,
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0xcc, 0x0a, 0xcc, 0x0a,
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x02, 0x63, 0x00,
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0x03, 0x88, 0x00, 0x4c
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};
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memcpy(data_, default_data, sizeof(default_data));
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memset(&data_[sizeof(default_data)], 0xff, sizeof(data_) - sizeof(default_data));
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}
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ClockStorage() {}
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/*!
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Advances the clock by 1 second.
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The caller should also signal an interrupt.
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The caller should also signal an interrupt if applicable.
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*/
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void update() {
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for(int c = 0; c < 4; ++c) {
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for(size_t c = 0; c < 4; ++c) {
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++seconds_[c];
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if(seconds_[c]) break;
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}
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}
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/*!
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Sets the current [P/B]RAM contents.
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*/
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template <typename CollectionT> void set_data(const CollectionT &collection) {
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set_data(collection.begin(), collection.end());
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}
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template <typename IteratorT> void set_data(IteratorT begin, const IteratorT end) {
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size_t c = 0;
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while(begin != end && c < 256) {
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data_[c] = *begin;
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++begin;
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++c;
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}
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}
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protected:
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static constexpr uint16_t NoResult = 0x100;
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static constexpr uint16_t DidComplete = 0x101;
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@ -92,7 +98,7 @@ class ClockStorage {
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case 0x30:
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// Either a register access or an extended instruction.
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if(command & 0x08) {
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address_ = (command & 0x7) << 5;
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address_ = unsigned((command & 0x7) << 5);
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phase_ = (command & 0x80) ? Phase::SecondAddressByteRead : Phase::SecondAddressByteWrite;
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return NoResult;
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} else {
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@ -162,10 +168,10 @@ class ClockStorage {
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private:
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uint8_t data_[256];
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uint8_t seconds_[4];
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uint8_t write_protect_;
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int address_;
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std::array<uint8_t, 256> data_{0xff};
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std::array<uint8_t, 4> seconds_{};
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uint8_t write_protect_ = 0;
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unsigned int address_ = 0;
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static constexpr int SecondsBuffer = 0x100;
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static constexpr int RegisterTest = 0x200;
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@ -257,7 +263,10 @@ class ParallelClock: public ClockStorage {
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// A no-op for now.
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} else {
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// Write to the RTC. Which in this implementation also sets up a future read.
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data_ = uint8_t(perform(data_));
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const auto result = perform(data_);
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if(result < 0x100) {
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data_ = uint8_t(result);
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}
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}
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// MAGIC! The transaction took 0 seconds.
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@ -82,7 +82,7 @@ template <typename Machine> class AuxiliaryMemorySwitches {
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bool read_auxiliary_memory = false;
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bool write_auxiliary_memory = false;
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bool internal_CX_rom = false;
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bool internal_CX_rom = true;
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bool slot_C3_rom = false;
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bool internal_C8_rom = false;
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@ -38,11 +38,40 @@
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#include <cassert>
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#include <array>
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//
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// HEAVY WARNING: THIS IS INCOMPLETE AND VERY PROVISIONAL.
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//
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// You'll notice lots of random bits of debugging code sitting around but commented out.
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// Most of this will go when this machine is complete. Please look past the gross ugliness
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// of this code's intermediate state if you are able.
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//
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namespace {
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constexpr int CLOCK_RATE = 14'318'180;
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class MemManagerChecker {
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// This is the first result that came up when searching for valid Apple IIgs BRAM states;
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// I'm unclear on its provenance.
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constexpr uint8_t default_bram[] = {
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0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x0d, 0x06, 0x02, 0x01, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x07, 0x06, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00, 0x0f, 0x06, 0x06, 0x00, 0x05, 0x06,
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0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x03, 0x02, 0x02, 0x02,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06,
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0x07, 0x00, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d,
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0x0e, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x96, 0x57, 0x3c,
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};
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/*class MemManagerChecker {
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int handle_total_ = 0;
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bool dump_bank(const Apple::IIgs::MemoryMap &memory, const char *name, uint32_t address, bool print, uint32_t must_contain = 0xffffffff) {
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const auto handles = memory.regions[memory.region_map[0xe117]].read;
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@ -149,7 +178,7 @@ class MemManagerChecker {
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return result;
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}
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};
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};*/
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}
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@ -187,6 +216,7 @@ class ConcreteMachine:
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set_clock_rate(double(CLOCK_RATE));
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speaker_.set_input_rate(float(CLOCK_RATE) / float(audio_divider));
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clock_.ClockStorage::set_data(std::begin(default_bram), std::end(default_bram));
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using Target = Analyser::Static::AppleIIgs::Target;
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ROM::Name system;
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@ -277,6 +307,11 @@ class ConcreteMachine:
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// std::srand(23);
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Memory::Fuzz(ram_);
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// Prior to ROM03 there's no power-on bit.
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if(target.model != Target::Model::ROM03) {
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speed_register_ &= ~0x40;
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}
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// Sync up initial values.
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memory_.set_speed_register(speed_register_ ^ 0x80);
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@ -348,6 +383,23 @@ class ConcreteMachine:
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static bool log = false;
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bool is_1Mhz = false;
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// if(operation == CPU::WDC65816::BusOperation::ReadOpcode) {
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// if(address == 0xfe00d5) {
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// printf("");
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// }
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//
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// printf("%06x a:%04x x:%04x y:%04x s:%04x d:%04x b:%04x\n",
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// address,
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// m65816_.get_value_of_register(CPU::WDC65816::Register::A),
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// m65816_.get_value_of_register(CPU::WDC65816::Register::X),
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// m65816_.get_value_of_register(CPU::WDC65816::Register::Y),
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//// m65816_.get_value_of_register(CPU::WDC65816::Register::Flags),
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// m65816_.get_value_of_register(CPU::WDC65816::Register::StackPointer),
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// m65816_.get_value_of_register(CPU::WDC65816::Register::Direct),
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// m65816_.get_value_of_register(CPU::WDC65816::Register::DataBank)
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// );
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// }
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if(operation == CPU::WDC65816::BusOperation::ReadVector && !(memory_.get_shadow_register()&0x40)) {
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// I think vector pulls always go to ROM?
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// That's slightly implied in the documentation, and doing so makes GS/OS boot, so...
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@ -936,9 +988,9 @@ class ConcreteMachine:
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// }
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if(operation == CPU::WDC65816::BusOperation::ReadOpcode) {
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if(total > 482342960 && total < 482352960 && address == 0xe10000) {
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printf("entry: %llu\n", static_cast<unsigned long long>(total));
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}
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// if(total > 482342960 && total < 482352960 && address == 0xe10000) {
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// printf("entry: %llu\n", static_cast<unsigned long long>(total));
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// }
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// log |= address == 0xfc144f;
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// log &= !((address < 0xfc144f) || (address >= 0xfc1490));
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@ -1147,3 +1199,4 @@ Machine *Machine::AppleIIgs(const Analyser::Static::Target *target, const ROMMac
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}
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Machine::~Machine() {}
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@ -241,7 +241,7 @@ class MemoryMap {
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friend AuxiliaryMemorySwitches;
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friend LanguageCardSwitches;
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uint8_t shadow_register_ = 0x08;
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uint8_t shadow_register_ = 0x00;
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uint8_t speed_register_ = 0x00;
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// MARK: - Memory banking.
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@ -49,6 +49,15 @@ namespace {
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constexpr int CLOCK_RATE = 7833600;
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// Former default PRAM:
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//
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// 0xa8, 0x00, 0x00, 0x00,
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// 0xcc, 0x0a, 0xcc, 0x0a,
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// 0x00, 0x00, 0x00, 0x00,
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// 0x00, 0x02, 0x63, 0x00,
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// 0x03, 0x88, 0x00, 0x4c
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}
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namespace Apple {
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