mirror of
https://github.com/TomHarte/CLK.git
synced 2024-06-29 15:29:36 +00:00
Reduces 68000 startup costs a little further.
This commit is contained in:
Thomas Harte
parent
d7883d18d4
commit
31edb15369
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@ -168,35 +168,66 @@ struct ProcessorStorageConstructor {
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then the corresponding effective address will be incremented or decremented
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by two after the cycle has completed.
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*/
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size_t assemble_program(std::string access_pattern, const std::vector<uint32_t *> &addresses = {}, bool read_full_words = true) {
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size_t assemble_program(const char *access_pattern, const std::vector<uint32_t *> &addresses = {}, bool read_full_words = true) {
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auto address_iterator = addresses.begin();
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using Action = BusStep::Action;
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std::vector<BusStep> steps;
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std::stringstream stream(access_pattern);
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// Tokenise the access pattern by splitting on spaces.
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std::string token;
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while(stream >> token) {
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const char *next_access_pattern = access_pattern;
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while(true) {
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/*
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Ugly C-style string parsing here:
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next_access_pattern is the end of the previous access pattern, i.e.
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it is where parsing should begin to find the next one.
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end_of_pattern will be where the current pattern ends, after any
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modifier suffixes have been removed.
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access_pattern is the beginning of the current pattern.
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Obiter: this replaces a std::stringstream >> std::string implementation,
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that was a lot cleaner but implied a lot of std::string constructions
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that made this section of code measureable slower. Which, inter alia,
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had a bit impact on the rate at which unit tests would run.
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So this ugliness is a net project improvement, I promise!
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*/
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while(*next_access_pattern == ' ') ++next_access_pattern;
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access_pattern = next_access_pattern;
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while(*next_access_pattern != ' ' && *next_access_pattern != '\0') ++next_access_pattern;
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if(next_access_pattern == access_pattern) break;
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const char *end_of_pattern = next_access_pattern;
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ProcessorBase::BusStep step;
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// Check for a plus-or-minus suffix.
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int post_adjustment = 0;
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if(token.back() == '-' || token.back() == '+') {
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if(token.back() == '-') {
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if(end_of_pattern[-1] == '-' || end_of_pattern[-1] == '+') {
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if(end_of_pattern[-1] == '-') {
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post_adjustment = -1;
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}
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if(token.back() == '+') {
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if(end_of_pattern[-1] == '+') {
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post_adjustment = 1;
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}
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token.pop_back();
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--end_of_pattern;
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}
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const auto token_length = end_of_pattern - access_pattern;
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// Do nothing (possibly twice).
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if(token == "n" || token == "nn") {
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if(token.size() == 2) {
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if(
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access_pattern[0] == 'n' &&
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(
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token_length == 1 ||
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(token_length == 2 && access_pattern[1] == 'n')
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)
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) {
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if(token_length == 2) {
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step.microcycle.length = HalfCycles(8);
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}
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steps.push_back(step);
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@ -204,7 +235,10 @@ struct ProcessorStorageConstructor {
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}
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// Do nothing, but with a length that definitely won't map it to the other do-nothings.
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if(token == "r") {
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if(
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access_pattern[0] == 'r' &&
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token_length == 1
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) {
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#ifndef NDEBUG
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// If this is a debug build, not where the resizeable microcycle is
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// (and double check that there's only the one).
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@ -215,51 +249,86 @@ struct ProcessorStorageConstructor {
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continue;
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}
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// Fetch SSP.
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if(token == "nF" || token == "nf") {
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step.microcycle.operation = Microcycle::NewAddress | Microcycle::Read | Microcycle::IsProgram; // IsProgram is a guess.
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step.microcycle.address = &storage_.effective_address_[0].full;
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step.microcycle.value = isupper(token[1]) ? &storage_.address_[7].halves.high : &storage_.address_[7].halves.low;
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steps.push_back(step);
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if(
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token_length == 2 &&
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access_pattern[0] == 'n'
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) {
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// Fetch SSP.
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if(tolower(access_pattern[1]) == 'f') {
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step.microcycle.operation = Microcycle::NewAddress | Microcycle::Read | Microcycle::IsProgram; // IsProgram is a guess.
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step.microcycle.address = &storage_.effective_address_[0].full;
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step.microcycle.value = isupper(access_pattern[1]) ? &storage_.address_[7].halves.high : &storage_.address_[7].halves.low;
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steps.push_back(step);
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step.microcycle.operation = Microcycle::SameAddress | Microcycle::Read | Microcycle::IsProgram | Microcycle::SelectWord;
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step.action = Action::IncrementEffectiveAddress0;
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steps.push_back(step);
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step.microcycle.operation = Microcycle::SameAddress | Microcycle::Read | Microcycle::IsProgram | Microcycle::SelectWord;
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step.action = Action::IncrementEffectiveAddress0;
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steps.push_back(step);
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continue;
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}
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continue;
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}
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// Fetch exception vector.
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if(token == "nV" || token == "nv") {
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step.microcycle.operation = Microcycle::NewAddress | Microcycle::Read | Microcycle::IsProgram; // IsProgram is a guess.
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step.microcycle.address = &storage_.effective_address_[0].full;
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step.microcycle.value = isupper(token[1]) ? &storage_.program_counter_.halves.high : &storage_.program_counter_.halves.low;
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steps.push_back(step);
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// Fetch exception vector.
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if(tolower(access_pattern[1]) == 'v') {
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step.microcycle.operation = Microcycle::NewAddress | Microcycle::Read | Microcycle::IsProgram; // IsProgram is a guess.
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step.microcycle.address = &storage_.effective_address_[0].full;
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step.microcycle.value = isupper(access_pattern[1]) ? &storage_.program_counter_.halves.high : &storage_.program_counter_.halves.low;
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steps.push_back(step);
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step.microcycle.operation = Microcycle::SameAddress | Microcycle::Read | Microcycle::IsProgram | Microcycle::SelectWord;
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step.action = Action::IncrementEffectiveAddress0;
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steps.push_back(step);
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step.microcycle.operation = Microcycle::SameAddress | Microcycle::Read | Microcycle::IsProgram | Microcycle::SelectWord;
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step.action = Action::IncrementEffectiveAddress0;
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steps.push_back(step);
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continue;
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}
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continue;
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}
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// Fetch from the program counter into the prefetch queue.
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if(token == "np") {
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step.microcycle.operation = Microcycle::NewAddress | Microcycle::Read | Microcycle::IsProgram;
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step.microcycle.address = &storage_.program_counter_.full;
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step.microcycle.value = &storage_.prefetch_queue_.halves.low;
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step.action = Action::AdvancePrefetch;
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steps.push_back(step);
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// Fetch from the program counter into the prefetch queue.
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if(access_pattern[1] == 'p') {
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step.microcycle.operation = Microcycle::NewAddress | Microcycle::Read | Microcycle::IsProgram;
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step.microcycle.address = &storage_.program_counter_.full;
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step.microcycle.value = &storage_.prefetch_queue_.halves.low;
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step.action = Action::AdvancePrefetch;
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steps.push_back(step);
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step.microcycle.operation = Microcycle::SameAddress | Microcycle::Read | Microcycle::IsProgram | Microcycle::SelectWord;
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step.action = Action::IncrementProgramCounter;
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steps.push_back(step);
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step.microcycle.operation = Microcycle::SameAddress | Microcycle::Read | Microcycle::IsProgram | Microcycle::SelectWord;
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step.action = Action::IncrementProgramCounter;
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steps.push_back(step);
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continue;
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continue;
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}
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// A stack write.
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if(tolower(access_pattern[1]) == 's') {
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step.microcycle.operation = Microcycle::NewAddress;
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step.microcycle.address = &storage_.effective_address_[1].full;
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step.microcycle.value = isupper(access_pattern[1]) ? &storage_.destination_bus_data_[0].halves.high : &storage_.destination_bus_data_[0].halves.low;
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steps.push_back(step);
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step.microcycle.operation = Microcycle::SameAddress | Microcycle::SelectWord;
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step.action = Action::DecrementEffectiveAddress1;
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steps.push_back(step);
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continue;
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}
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// A stack read.
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if(tolower(access_pattern[1]) == 'u') {
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RegisterPair32 *const scratch_data = &storage_.source_bus_data_[0];
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step.microcycle.operation = Microcycle::NewAddress | Microcycle::Read;
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step.microcycle.address = &storage_.effective_address_[0].full;
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step.microcycle.value = isupper(access_pattern[1]) ? &scratch_data->halves.high : &scratch_data->halves.low;
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steps.push_back(step);
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step.microcycle.operation = Microcycle::SameAddress | Microcycle::Read | Microcycle::SelectWord;
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step.action = Action::IncrementEffectiveAddress0;
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steps.push_back(step);
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continue;
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}
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}
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// The reset cycle.
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if(token == "_") {
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if(token_length == 1 && access_pattern[0] == '_') {
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step.microcycle.length = HalfCycles(248);
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step.microcycle.operation = Microcycle::Reset;
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steps.push_back(step);
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@ -268,22 +337,32 @@ struct ProcessorStorageConstructor {
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}
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// A standard read or write.
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if(token == "nR" || token == "nr" || token == "nW" || token == "nw" || token == "nRd" || token == "nrd" || token == "nWr" || token == "nwr") {
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const bool is_read = tolower(token[1]) == 'r';
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const bool use_source_storage = (token == "nR" || token == "nr" || token == "nWr" || token == "nwr");
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if(
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access_pattern[0] == 'n' &&
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(tolower(access_pattern[1]) == 'r' || tolower(access_pattern[1]) == 'w') &&
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(
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token_length == 2 ||
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(
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token_length == 3 &&
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(access_pattern[2] == 'd' || access_pattern[2] == 'r')
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)
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)
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) {
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const bool is_read = tolower(access_pattern[1]) == 'r';
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const bool use_source_storage = tolower(end_of_pattern[-1]) == 'r';
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RegisterPair32 *const scratch_data = use_source_storage ? &storage_.source_bus_data_[0] : &storage_.destination_bus_data_[0];
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assert(address_iterator != addresses.end());
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step.microcycle.operation = Microcycle::NewAddress | (is_read ? Microcycle::Read : 0);
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step.microcycle.address = *address_iterator;
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step.microcycle.value = isupper(token[1]) ? &scratch_data->halves.high : &scratch_data->halves.low;
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step.microcycle.value = isupper(access_pattern[1]) ? &scratch_data->halves.high : &scratch_data->halves.low;
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steps.push_back(step);
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step.microcycle.operation = Microcycle::SameAddress | (is_read ? Microcycle::Read : 0) | (read_full_words ? Microcycle::SelectWord : Microcycle::SelectByte);
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if(post_adjustment) {
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// nr and nR should affect address 0; nw, nW, nrd and nRd should affect address 1.
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if(tolower(token[1]) == 'r' && token.size() == 2) {
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if(tolower(access_pattern[1]) == 'r' && token_length == 2) {
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step.action = (post_adjustment > 0) ? Action::IncrementEffectiveAddress0 : Action::DecrementEffectiveAddress0;
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} else {
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step.action = (post_adjustment > 0) ? Action::IncrementEffectiveAddress1 : Action::DecrementEffectiveAddress1;
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@ -296,70 +375,42 @@ struct ProcessorStorageConstructor {
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continue;
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}
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// The completing part of a TAS.
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if(token == "tas") {
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RegisterPair32 *const scratch_data = &storage_.destination_bus_data_[0];
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if(token_length == 3) {
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// The completing part of a TAS.
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if(access_pattern[0] == 't' && access_pattern[1] == 'a' && access_pattern[2] == 's') {
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RegisterPair32 *const scratch_data = &storage_.destination_bus_data_[0];
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assert(address_iterator != addresses.end());
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assert(address_iterator != addresses.end());
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step.microcycle.length = HalfCycles(9);
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step.microcycle.operation = Microcycle::SameAddress;
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step.microcycle.address = *address_iterator;
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step.microcycle.value = &scratch_data->halves.low;
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steps.push_back(step);
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step.microcycle.length = HalfCycles(9);
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step.microcycle.operation = Microcycle::SameAddress;
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step.microcycle.address = *address_iterator;
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step.microcycle.value = &scratch_data->halves.low;
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steps.push_back(step);
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step.microcycle.length = HalfCycles(3);
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step.microcycle.operation = Microcycle::SameAddress | Microcycle::SelectByte;
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steps.push_back(step);
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++address_iterator;
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step.microcycle.length = HalfCycles(3);
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step.microcycle.operation = Microcycle::SameAddress | Microcycle::SelectByte;
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steps.push_back(step);
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++address_iterator;
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continue;
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continue;
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}
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// Interrupt acknowledge.
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if(access_pattern[0] == 'i' && access_pattern[1] == 'n' && access_pattern[2] == 't') {
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step.microcycle.operation = Microcycle::InterruptAcknowledge | Microcycle::NewAddress;
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step.microcycle.address = &storage_.effective_address_[0].full; // The selected interrupt should be in bits 1–3; but 0 should be set.
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step.microcycle.value = &storage_.source_bus_data_[0].halves.low;
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steps.push_back(step);
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step.microcycle.operation = Microcycle::InterruptAcknowledge | Microcycle::SameAddress | Microcycle::SelectByte;
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steps.push_back(step);
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continue;
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}
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}
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// A stack write.
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if(token == "nS" || token == "ns") {
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step.microcycle.operation = Microcycle::NewAddress;
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step.microcycle.address = &storage_.effective_address_[1].full;
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step.microcycle.value = isupper(token[1]) ? &storage_.destination_bus_data_[0].halves.high : &storage_.destination_bus_data_[0].halves.low;
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steps.push_back(step);
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step.microcycle.operation = Microcycle::SameAddress | Microcycle::SelectWord;
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step.action = Action::DecrementEffectiveAddress1;
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steps.push_back(step);
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continue;
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}
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// A stack read.
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if(token == "nU" || token == "nu") {
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RegisterPair32 *const scratch_data = &storage_.source_bus_data_[0];
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step.microcycle.operation = Microcycle::NewAddress | Microcycle::Read;
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step.microcycle.address = &storage_.effective_address_[0].full;
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step.microcycle.value = isupper(token[1]) ? &scratch_data->halves.high : &scratch_data->halves.low;
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steps.push_back(step);
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step.microcycle.operation = Microcycle::SameAddress | Microcycle::Read | Microcycle::SelectWord;
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step.action = Action::IncrementEffectiveAddress0;
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steps.push_back(step);
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continue;
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}
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// Interrupt acknowledge.
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if(token == "int") {
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step.microcycle.operation = Microcycle::InterruptAcknowledge | Microcycle::NewAddress;
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step.microcycle.address = &storage_.effective_address_[0].full; // The selected interrupt should be in bits 1–3; but 0 should be set.
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step.microcycle.value = &storage_.source_bus_data_[0].halves.low;
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steps.push_back(step);
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step.microcycle.operation = Microcycle::InterruptAcknowledge | Microcycle::SameAddress | Microcycle::SelectByte;
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steps.push_back(step);
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continue;
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}
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std::cerr << "MC68000 program builder; Unknown access token " << token << std::endl;
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std::cerr << "MC68000 program builder; Unknown access token " << std::string(access_pattern, end_of_pattern) << std::endl;
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assert(false);
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}
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@ -3127,8 +3178,8 @@ CPU::MC68000::ProcessorStorage::ProcessorStorage() {
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}
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movem_reads_pattern += "nr";
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addresses.push_back(nullptr);
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const size_t movem_read_offset = constructor.assemble_program(movem_reads_pattern, addresses);
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const size_t movem_write_offset = constructor.assemble_program(movem_writes_pattern, addresses);
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const size_t movem_read_offset = constructor.assemble_program(movem_reads_pattern.c_str(), addresses);
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const size_t movem_write_offset = constructor.assemble_program(movem_writes_pattern.c_str(), addresses);
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// Target addresses and values will be filled in by TRAP/illegal too.
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const size_t trap_offset = constructor.assemble_program("r nw nw nW nV nv np np", { &precomputed_addresses_[0], &precomputed_addresses_[1], &precomputed_addresses_[2] });
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