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https://github.com/TomHarte/CLK.git
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Fixed: paging is based directly on the access, independent of the read/write line (since it isn't actually exposed to catridges).
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59c872ada6
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@ -269,29 +269,29 @@ int Machine::perform_bus_operation(CPU6502::BusOperation operation, uint16_t add
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if(operation != CPU6502::BusOperation::Ready) {
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if(operation != CPU6502::BusOperation::Ready) {
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// check for a ROM or paging access
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// check for a paging access
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if ((address&0x1000) && isReadOperation(operation)) {
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if(_rom_size > 4096 && ((address & 0x1f00) == 0x1f00)) {
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uint8_t *base_ptr = _romPages[0];
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uint8_t first_paging_register = 0xf8 - (_rom_size >> 14)*2;
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if(_rom_size > 4096 && ((address & 0x1f00) == 0x1f00)) {
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const uint8_t paging_register = address&0xff;
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uint8_t *base_ptr = _romPages[0];
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if(paging_register >= first_paging_register) {
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uint8_t first_paging_register = 0xf8 - (_rom_size >> 14)*2;
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const uint16_t selected_page = paging_register - first_paging_register;
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if(selected_page * 4096 < _rom_size) {
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const uint8_t paging_register = address&0xff;
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base_ptr = &_rom[selected_page * 4096];
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if(paging_register >= first_paging_register) {
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const uint16_t selected_page = paging_register - first_paging_register;
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if(selected_page * 4096 < _rom_size) {
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base_ptr = &_rom[selected_page * 4096];
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}
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}
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if(base_ptr != _romPages[0]) {
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_romPages[0] = base_ptr;
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_romPages[1] = base_ptr + 1024;
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_romPages[2] = base_ptr + 2048;
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_romPages[3] = base_ptr + 3072;
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}
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}
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}
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}
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if(base_ptr != _romPages[0]) {
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_romPages[0] = base_ptr;
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_romPages[1] = base_ptr + 1024;
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_romPages[2] = base_ptr + 2048;
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_romPages[3] = base_ptr + 3072;
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}
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}
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// check for a ROM read
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if ((address&0x1000) && isReadOperation(operation)) {
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returnValue &= _romPages[(address >> 10)&3][address&1023];
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returnValue &= _romPages[(address >> 10)&3][address&1023];
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}
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}
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