mirror of
https://github.com/TomHarte/CLK.git
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Merge pull request #902 from TomHarte/Z80Lines
Spell out, test and correct Z80 bus activity.
This commit is contained in:
Thomas Harte
GitHub
commit
325e2b3941
@ -917,6 +917,7 @@
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4BDA00E022E644AF00AC3CD0 /* CSROMReceiverView.m in Sources */ = {isa = PBXBuildFile; fileRef = 4BDA00DF22E644AF00AC3CD0 /* CSROMReceiverView.m */; };
|
||||
4BDA00E422E663B900AC3CD0 /* NSData+CRC32.m in Sources */ = {isa = PBXBuildFile; fileRef = 4BDA00E222E663B900AC3CD0 /* NSData+CRC32.m */; };
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4BDA00E622E699B000AC3CD0 /* CSMachine.mm in Sources */ = {isa = PBXBuildFile; fileRef = 4B2A53961D117D36003C6002 /* CSMachine.mm */; };
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4BDA8235261E8E000021AA19 /* Z80ContentionTests.mm in Sources */ = {isa = PBXBuildFile; fileRef = 4BDA8234261E8E000021AA19 /* Z80ContentionTests.mm */; };
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4BDACBEC22FFA5D20045EF7E /* ncr5380.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4BDACBEA22FFA5D20045EF7E /* ncr5380.cpp */; };
|
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4BDACBED22FFA5D20045EF7E /* ncr5380.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4BDACBEA22FFA5D20045EF7E /* ncr5380.cpp */; };
|
||||
4BDB61EB2032806E0048AF91 /* CSAtari2600.mm in Sources */ = {isa = PBXBuildFile; fileRef = 4B2A539A1D117D36003C6002 /* CSAtari2600.mm */; };
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@ -1934,6 +1935,7 @@
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4BDA00DF22E644AF00AC3CD0 /* CSROMReceiverView.m */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.objc; path = CSROMReceiverView.m; sourceTree = "<group>"; };
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4BDA00E222E663B900AC3CD0 /* NSData+CRC32.m */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.objc; path = "NSData+CRC32.m"; sourceTree = "<group>"; };
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4BDA00E322E663B900AC3CD0 /* NSData+CRC32.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = "NSData+CRC32.h"; sourceTree = "<group>"; };
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4BDA8234261E8E000021AA19 /* Z80ContentionTests.mm */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.objcpp; path = Z80ContentionTests.mm; sourceTree = "<group>"; };
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4BDACBEA22FFA5D20045EF7E /* ncr5380.cpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.cpp; path = ncr5380.cpp; sourceTree = "<group>"; };
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4BDACBEB22FFA5D20045EF7E /* ncr5380.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = ncr5380.hpp; sourceTree = "<group>"; };
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4BDB3D8522833321002D3CEE /* Keyboard.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = Keyboard.hpp; sourceTree = "<group>"; };
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@ -3964,6 +3966,7 @@
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4B2AF8681E513FC20027EE29 /* TIATests.mm */,
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4B1D08051E0F7A1100763741 /* TimeTests.mm */,
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4BEE4BD325A26E2B00011BD2 /* x86DecoderTests.mm */,
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4BDA8234261E8E000021AA19 /* Z80ContentionTests.mm */,
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4BB73EB81B587A5100552FC2 /* Info.plist */,
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4BC9E1ED1D23449A003FCEE4 /* 6502InterruptTests.swift */,
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4B92EAC91B7C112B00246143 /* 6502TimingTests.swift */,
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@ -5649,6 +5652,7 @@
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4B9D0C4B22C7D70A00DE1AD3 /* 68000BCDTests.mm in Sources */,
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4B778F5E23A5F3230000D260 /* Oric.cpp in Sources */,
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4B3BA0C31D318AEC005DD7A7 /* C1540Tests.swift in Sources */,
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4BDA8235261E8E000021AA19 /* Z80ContentionTests.mm in Sources */,
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4B778F1A23A5ED320000D260 /* Video.cpp in Sources */,
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4B778F3B23A5F1650000D260 /* KeyboardMachine.cpp in Sources */,
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4B778F2E23A5F09E0000D260 /* IRQDelegatePortHandler.cpp in Sources */,
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1472
OSBindings/Mac/Clock SignalTests/Z80ContentionTests.mm
Normal file
1472
OSBindings/Mac/Clock SignalTests/Z80ContentionTests.mm
Normal file
File diff suppressed because it is too large
Load Diff
@ -82,24 +82,25 @@ template < class T,
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}
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number_of_cycles_ -= operation->machine_cycle.length;
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last_request_status_ = request_status_;
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// TODO: eliminate this conditional if all bus cycles have an address filled in.
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last_address_bus_ = operation->machine_cycle.address ? *operation->machine_cycle.address : 0xdead;
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number_of_cycles_ -= bus_handler_.perform_machine_cycle(operation->machine_cycle);
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if(uses_bus_request && bus_request_line_) goto do_bus_acknowledge;
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break;
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case MicroOp::MoveToNextProgram:
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advance_operation();
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break;
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case MicroOp::DecodeOperation:
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case MicroOp::IncrementR:
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refresh_addr_ = ir_;
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ir_.halves.low = (ir_.halves.low & 0x80) | ((ir_.halves.low + current_instruction_page_->r_step) & 0x7f);
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ir_.halves.low = (ir_.halves.low & 0x80) | ((ir_.halves.low + 1) & 0x7f);
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break;
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case MicroOp::DecodeOperation:
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pc_.full += pc_increment_ & uint16_t(halt_mask_);
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scheduled_program_counter_ = current_instruction_page_->instructions[operation_ & halt_mask_];
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flag_adjustment_history_ <<= 1;
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break;
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case MicroOp::DecodeOperationNoRChange:
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refresh_addr_ = ir_;
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pc_.full += pc_increment_ & uint16_t(halt_mask_);
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scheduled_program_counter_ = current_instruction_page_->instructions[operation_ & halt_mask_];
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break;
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case MicroOp::Increment8NoFlags: ++ *static_cast<uint8_t *>(operation->source); break;
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case MicroOp::Increment16: ++ *static_cast<uint16_t *>(operation->source); break;
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@ -927,7 +928,7 @@ template < class T,
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return wait_line_;
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}
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#define isTerminal(n) (n == MicroOp::MoveToNextProgram || n == MicroOp::DecodeOperation || n == MicroOp::DecodeOperationNoRChange)
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#define isTerminal(n) (n == MicroOp::MoveToNextProgram || n == MicroOp::DecodeOperation)
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template < class T,
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bool uses_bus_request,
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@ -20,14 +20,14 @@ ProcessorStorage::ProcessorStorage() {
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#define ReadOpcodeWait(f) PartialMachineCycle(PartialMachineCycle::ReadOpcodeWait, HalfCycles(2), &pc_.full, &operation_, f)
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#define ReadOpcodeEnd() PartialMachineCycle(PartialMachineCycle::ReadOpcode, HalfCycles(1), &pc_.full, &operation_, false)
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#define Refresh(len) PartialMachineCycle(PartialMachineCycle::Refresh, HalfCycles(len), &refresh_addr_.full, nullptr, false)
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#define Refresh() PartialMachineCycle(PartialMachineCycle::Refresh, HalfCycles(4), &refresh_addr_.full, nullptr, false)
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#define ReadStart(addr, val) PartialMachineCycle(PartialMachineCycle::ReadStart, HalfCycles(3), &addr.full, &val, false)
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#define ReadWait(l, addr, val, f) PartialMachineCycle(PartialMachineCycle::ReadWait, HalfCycles(l), &addr.full, &val, f)
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#define ReadWait(addr, val) PartialMachineCycle(PartialMachineCycle::ReadWait, HalfCycles(2), &addr.full, &val, true)
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#define ReadEnd(addr, val) PartialMachineCycle(PartialMachineCycle::Read, HalfCycles(3), &addr.full, &val, false)
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#define WriteStart(addr, val) PartialMachineCycle(PartialMachineCycle::WriteStart,HalfCycles(3), &addr.full, &val, false)
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#define WriteWait(l, addr, val, f) PartialMachineCycle(PartialMachineCycle::WriteWait, HalfCycles(l), &addr.full, &val, f)
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#define WriteWait(addr, val) PartialMachineCycle(PartialMachineCycle::WriteWait, HalfCycles(2), &addr.full, &val, true)
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#define WriteEnd(addr, val) PartialMachineCycle(PartialMachineCycle::Write, HalfCycles(3), &addr.full, &val, false)
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#define InputStart(addr, val) PartialMachineCycle(PartialMachineCycle::InputStart, HalfCycles(3), &addr.full, &val, false)
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@ -47,32 +47,15 @@ ProcessorStorage::ProcessorStorage() {
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#define BusOp(op) {MicroOp::BusOperation, nullptr, nullptr, op}
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// Compound bus operations, as micro-ops
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// Read3 is a standard read cycle: 1.5 cycles, then check the wait line, then 1.5 cycles;
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// Read4 is a four-cycle read that has to do something to calculate the address: 1.5 cycles, then an extra wait cycle, then check the wait line, then 1.5 cycles;
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// Read4Pre is a four-cycle read that has to do something after reading: 1.5 cycles, then check the wait line, then an extra wait cycle, then 1.5 cycles;
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// Read5 is a five-cycle read: 1.5 cycles, two wait cycles, check the wait line, 1.5 cycles.
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#define Read3(addr, val) BusOp(ReadStart(addr, val)), BusOp(ReadWait(2, addr, val, true)), BusOp(ReadEnd(addr, val))
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#define Read4(addr, val) BusOp(ReadStart(addr, val)), BusOp(ReadWait(2, addr, val, false)), BusOp(ReadWait(2, addr, val, true)), BusOp(ReadEnd(addr, val))
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#define Read4Pre(addr, val) BusOp(ReadStart(addr, val)), BusOp(ReadWait(2, addr, val, true)), BusOp(ReadWait(2, addr, val, false)), BusOp(ReadEnd(addr, val))
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#define Read5(addr, val) BusOp(ReadStart(addr, val)), BusOp(ReadWait(4, addr, val, false)), BusOp(ReadWait(2, addr, val, true)), BusOp(ReadEnd(addr, val))
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#define Write3(addr, val) BusOp(WriteStart(addr, val)), BusOp(WriteWait(2, addr, val, true)), BusOp(WriteEnd(addr, val))
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#define Write5(addr, val) BusOp(WriteStart(addr, val)), BusOp(WriteWait(4, addr, val, false)), BusOp(WriteWait(2, addr, val, true)), BusOp(WriteEnd(addr, val))
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#define Input(addr, val) BusOp(InputStart(addr, val)), BusOp(InputWait(addr, val, false)), BusOp(InputWait(addr, val, true)), BusOp(InputEnd(addr, val))
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#define Output(addr, val) BusOp(OutputStart(addr, val)), BusOp(OutputWait(addr, val, false)), BusOp(OutputWait(addr, val, true)), BusOp(OutputEnd(addr, val))
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#define InternalOperation(len) {MicroOp::BusOperation, nullptr, nullptr, {PartialMachineCycle::Internal, HalfCycles(len), nullptr, nullptr, false}}
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#define InternalOperation(len) {MicroOp::BusOperation, nullptr, nullptr, {PartialMachineCycle::Internal, HalfCycles(len), &last_address_bus_, nullptr, false}}
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#define Read(addr, val) BusOp(ReadStart(addr, val)), BusOp(ReadWait(addr, val)), BusOp(ReadEnd(addr, val))
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#define Write(addr, val) BusOp(WriteStart(addr, val)), BusOp(WriteWait(addr, val)), BusOp(WriteEnd(addr, val))
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#define Input(addr, val) BusOp(InputStart(addr, val)), BusOp(InputWait(addr, val, false)), BusOp(InputWait(addr, val, true)), BusOp(InputEnd(addr, val))
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#define Output(addr, val) BusOp(OutputStart(addr, val)), BusOp(OutputWait(addr, val, false)), BusOp(OutputWait(addr, val, true)), BusOp(OutputEnd(addr, val))
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/// A sequence is a series of micro-ops that ends in a move-to-next-program operation.
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#define Sequence(...) { __VA_ARGS__, {MicroOp::MoveToNextProgram} }
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/// An instruction is the part of an instruction that follows instruction fetch; it should include two or more refresh cycles and then the work of the instruction.
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#define Instr(r, ...) Sequence(BusOp(Refresh(r)), __VA_ARGS__)
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/// A standard instruction is one with the most normal timing: two cycles of refresh, then the work.
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#define StdInstr(...) Instr(4, __VA_ARGS__)
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// Assumption made: those instructions that are rated with an opcode fetch greater than four cycles spend the extra time
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// providing a lengthened refresh cycle. I assume this because the CPU doesn't have foresight and presumably spends the
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// normal refresh time decoding. So if it gets to cycle four and realises it has two more cycles of work, I have assumed
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@ -82,65 +65,60 @@ ProcessorStorage::ProcessorStorage() {
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#define Inc16(r) {(&r == &pc_) ? MicroOp::IncrementPC : MicroOp::Increment16, &r.full}
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#define Inc8NoFlags(r) {MicroOp::Increment8NoFlags, &r}
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#define ReadInc(addr, val) Read3(addr, val), Inc16(addr)
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#define Read4Inc(addr, val) Read4(addr, val), Inc16(addr)
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#define Read5Inc(addr, val) Read5(addr, val), Inc16(addr)
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#define WriteInc(addr, val) Write3(addr, val), {MicroOp::Increment16, &addr.full}
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#define ReadInc(addr, val) Read(addr, val), Inc16(addr)
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#define WriteInc(addr, val) Write(addr, val), {MicroOp::Increment16, &addr.full}
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#define Read16Inc(addr, val) ReadInc(addr, val.halves.low), ReadInc(addr, val.halves.high)
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#define Read16(addr, val) ReadInc(addr, val.halves.low), Read3(addr, val.halves.high)
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#define Read16(addr, val) ReadInc(addr, val.halves.low), Read(addr, val.halves.high)
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#define Write16(addr, val) WriteInc(addr, val.halves.low), Write3(addr, val.halves.high)
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#define Write16(addr, val) WriteInc(addr, val.halves.low), Write(addr, val.halves.high)
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#define INDEX() {MicroOp::IndexedPlaceHolder}, ReadInc(pc_, temp8_), InternalOperation(10), {MicroOp::CalculateIndexAddress, &index}
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#define FINDEX() {MicroOp::IndexedPlaceHolder}, ReadInc(pc_, temp8_), {MicroOp::CalculateIndexAddress, &index}
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#define INDEX_ADDR() (add_offsets ? memptr_ : index)
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#define Push(x) {MicroOp::Decrement16, &sp_.full}, Write3(sp_, x.halves.high), {MicroOp::Decrement16, &sp_.full}, Write3(sp_, x.halves.low)
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#define Pop(x) Read3(sp_, x.halves.low), {MicroOp::Increment16, &sp_.full}, Read3(sp_, x.halves.high), {MicroOp::Increment16, &sp_.full}
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#define Push8(x) {MicroOp::Decrement16, &sp_.full}, Write3(sp_, x.halves.high), {MicroOp::Decrement16, &sp_.full}, Write5(sp_, x.halves.low)
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#define Pop7(x) Read3(sp_, x.halves.low), {MicroOp::Increment16, &sp_.full}, Read4(sp_, x.halves.high), {MicroOp::Increment16, &sp_.full}
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#define Push(x) {MicroOp::Decrement16, &sp_.full}, Write(sp_, x.halves.high), {MicroOp::Decrement16, &sp_.full}, Write(sp_, x.halves.low)
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#define Pop(x) Read(sp_, x.halves.low), {MicroOp::Increment16, &sp_.full}, Read(sp_, x.halves.high), {MicroOp::Increment16, &sp_.full}
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/* The following are actual instructions */
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#define NOP Sequence(BusOp(Refresh(4)))
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#define NOP { {MicroOp::MoveToNextProgram} }
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#define JP(cc) StdInstr(Read16Inc(pc_, memptr_), {MicroOp::cc, nullptr}, {MicroOp::Move16, &memptr_.full, &pc_.full})
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#define CALL(cc) StdInstr(ReadInc(pc_, memptr_.halves.low), {MicroOp::cc, conditional_call_untaken_program_.data()}, Read4Inc(pc_, memptr_.halves.high), Push(pc_), {MicroOp::Move16, &memptr_.full, &pc_.full})
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#define RET(cc) Instr(6, {MicroOp::cc, nullptr}, Pop(memptr_), {MicroOp::Move16, &memptr_.full, &pc_.full})
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#define JR(cc) StdInstr(ReadInc(pc_, temp8_), {MicroOp::cc, nullptr}, InternalOperation(10), {MicroOp::CalculateIndexAddress, &pc_.full}, {MicroOp::Move16, &memptr_.full, &pc_.full})
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#define RST() Instr(6, {MicroOp::CalculateRSTDestination}, Push(pc_), {MicroOp::Move16, &memptr_.full, &pc_.full})
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#define LD(a, b) StdInstr({MicroOp::Move8, &b, &a})
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#define JP(cc) Sequence(Read16Inc(pc_, memptr_), {MicroOp::cc, nullptr}, {MicroOp::Move16, &memptr_.full, &pc_.full})
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#define CALL(cc) Sequence(ReadInc(pc_, memptr_.halves.low), {MicroOp::cc, conditional_call_untaken_program_.data()}, ReadInc(pc_, memptr_.halves.high), InternalOperation(2), Push(pc_), {MicroOp::Move16, &memptr_.full, &pc_.full})
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#define RET(cc) Sequence(InternalOperation(2), {MicroOp::cc, nullptr}, Pop(memptr_), {MicroOp::Move16, &memptr_.full, &pc_.full})
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#define JR(cc) Sequence(ReadInc(pc_, temp8_), {MicroOp::cc, nullptr}, InternalOperation(10), {MicroOp::CalculateIndexAddress, &pc_.full}, {MicroOp::Move16, &memptr_.full, &pc_.full})
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#define RST() Sequence(InternalOperation(2), {MicroOp::CalculateRSTDestination}, Push(pc_), {MicroOp::Move16, &memptr_.full, &pc_.full})
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#define LD(a, b) Sequence({MicroOp::Move8, &b, &a})
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#define LD_GROUP(r, ri) \
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LD(r, bc_.halves.high), LD(r, bc_.halves.low), LD(r, de_.halves.high), LD(r, de_.halves.low), \
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LD(r, index.halves.high), LD(r, index.halves.low), \
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StdInstr(INDEX(), Read3(INDEX_ADDR(), temp8_), {MicroOp::Move8, &temp8_, &ri}), \
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Sequence(INDEX(), Read(INDEX_ADDR(), temp8_), {MicroOp::Move8, &temp8_, &ri}), \
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LD(r, a_)
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#define READ_OP_GROUP(op) \
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StdInstr({MicroOp::op, &bc_.halves.high}), StdInstr({MicroOp::op, &bc_.halves.low}), \
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StdInstr({MicroOp::op, &de_.halves.high}), StdInstr({MicroOp::op, &de_.halves.low}), \
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StdInstr({MicroOp::op, &index.halves.high}), StdInstr({MicroOp::op, &index.halves.low}), \
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StdInstr(INDEX(), Read3(INDEX_ADDR(), temp8_), {MicroOp::op, &temp8_}), \
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StdInstr({MicroOp::op, &a_})
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Sequence({MicroOp::op, &bc_.halves.high}), Sequence({MicroOp::op, &bc_.halves.low}), \
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Sequence({MicroOp::op, &de_.halves.high}), Sequence({MicroOp::op, &de_.halves.low}), \
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Sequence({MicroOp::op, &index.halves.high}), Sequence({MicroOp::op, &index.halves.low}), \
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Sequence(INDEX(), Read(INDEX_ADDR(), temp8_), {MicroOp::op, &temp8_}), \
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Sequence({MicroOp::op, &a_})
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#define READ_OP_GROUP_D(op) \
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StdInstr({MicroOp::op, &bc_.halves.high}), StdInstr({MicroOp::op, &bc_.halves.low}), \
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StdInstr({MicroOp::op, &de_.halves.high}), StdInstr({MicroOp::op, &de_.halves.low}), \
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StdInstr({MicroOp::op, &index.halves.high}), StdInstr({MicroOp::op, &index.halves.low}), \
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StdInstr(INDEX(), Read4Pre(INDEX_ADDR(), temp8_), {MicroOp::op, &temp8_}), \
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StdInstr({MicroOp::op, &a_})
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Sequence({MicroOp::op, &bc_.halves.high}), Sequence({MicroOp::op, &bc_.halves.low}), \
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Sequence({MicroOp::op, &de_.halves.high}), Sequence({MicroOp::op, &de_.halves.low}), \
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Sequence({MicroOp::op, &index.halves.high}), Sequence({MicroOp::op, &index.halves.low}), \
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Sequence(INDEX(), Read(INDEX_ADDR(), temp8_), InternalOperation(2), {MicroOp::op, &temp8_}), \
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Sequence({MicroOp::op, &a_})
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#define RMW(x, op, ...) StdInstr(INDEX(), Read4Pre(INDEX_ADDR(), x), {MicroOp::op, &x}, Write3(INDEX_ADDR(), x))
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#define RMWI(x, op, ...) StdInstr(Read4(INDEX_ADDR(), x), {MicroOp::op, &x}, Write3(INDEX_ADDR(), x))
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#define RMW(x, op, ...) Sequence(INDEX(), Read(INDEX_ADDR(), x), InternalOperation(2), {MicroOp::op, &x}, Write(INDEX_ADDR(), x))
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#define RMWI(x, op, ...) Sequence(Read(INDEX_ADDR(), x), InternalOperation(2), {MicroOp::op, &x}, Write(INDEX_ADDR(), x))
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#define MODIFY_OP_GROUP(op) \
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StdInstr({MicroOp::op, &bc_.halves.high}), StdInstr({MicroOp::op, &bc_.halves.low}), \
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StdInstr({MicroOp::op, &de_.halves.high}), StdInstr({MicroOp::op, &de_.halves.low}), \
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StdInstr({MicroOp::op, &index.halves.high}), StdInstr({MicroOp::op, &index.halves.low}), \
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Sequence({MicroOp::op, &bc_.halves.high}), Sequence({MicroOp::op, &bc_.halves.low}), \
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Sequence({MicroOp::op, &de_.halves.high}), Sequence({MicroOp::op, &de_.halves.low}), \
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Sequence({MicroOp::op, &index.halves.high}), Sequence({MicroOp::op, &index.halves.low}), \
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RMW(temp8_, op), \
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StdInstr({MicroOp::op, &a_})
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||||
Sequence({MicroOp::op, &a_})
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||||
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||||
#define IX_MODIFY_OP_GROUP(op) \
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RMWI(bc_.halves.high, op), \
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@ -153,18 +131,18 @@ ProcessorStorage::ProcessorStorage() {
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||||
RMWI(a_, op)
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||||
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||||
#define IX_READ_OP_GROUP(op) \
|
||||
StdInstr(Read4(INDEX_ADDR(), temp8_), {MicroOp::op, &temp8_}), \
|
||||
StdInstr(Read4(INDEX_ADDR(), temp8_), {MicroOp::op, &temp8_}), \
|
||||
StdInstr(Read4(INDEX_ADDR(), temp8_), {MicroOp::op, &temp8_}), \
|
||||
StdInstr(Read4(INDEX_ADDR(), temp8_), {MicroOp::op, &temp8_}), \
|
||||
StdInstr(Read4(INDEX_ADDR(), temp8_), {MicroOp::op, &temp8_}), \
|
||||
StdInstr(Read4(INDEX_ADDR(), temp8_), {MicroOp::op, &temp8_}), \
|
||||
StdInstr(Read4(INDEX_ADDR(), temp8_), {MicroOp::op, &temp8_}), \
|
||||
StdInstr(Read4(INDEX_ADDR(), temp8_), {MicroOp::op, &temp8_})
|
||||
Sequence(Read(INDEX_ADDR(), temp8_), InternalOperation(2), {MicroOp::op, &temp8_}), \
|
||||
Sequence(Read(INDEX_ADDR(), temp8_), InternalOperation(2), {MicroOp::op, &temp8_}), \
|
||||
Sequence(Read(INDEX_ADDR(), temp8_), InternalOperation(2), {MicroOp::op, &temp8_}), \
|
||||
Sequence(Read(INDEX_ADDR(), temp8_), InternalOperation(2), {MicroOp::op, &temp8_}), \
|
||||
Sequence(Read(INDEX_ADDR(), temp8_), InternalOperation(2), {MicroOp::op, &temp8_}), \
|
||||
Sequence(Read(INDEX_ADDR(), temp8_), InternalOperation(2), {MicroOp::op, &temp8_}), \
|
||||
Sequence(Read(INDEX_ADDR(), temp8_), InternalOperation(2), {MicroOp::op, &temp8_}), \
|
||||
Sequence(Read(INDEX_ADDR(), temp8_), InternalOperation(2), {MicroOp::op, &temp8_})
|
||||
|
||||
#define ADD16(d, s) StdInstr(InternalOperation(8), InternalOperation(6), {MicroOp::ADD16, &s.full, &d.full})
|
||||
#define ADC16(d, s) StdInstr(InternalOperation(8), InternalOperation(6), {MicroOp::ADC16, &s.full, &d.full})
|
||||
#define SBC16(d, s) StdInstr(InternalOperation(8), InternalOperation(6), {MicroOp::SBC16, &s.full, &d.full})
|
||||
#define ADD16(d, s) Sequence(InternalOperation(8), InternalOperation(6), {MicroOp::ADD16, &s.full, &d.full})
|
||||
#define ADC16(d, s) Sequence(InternalOperation(8), InternalOperation(6), {MicroOp::ADC16, &s.full, &d.full})
|
||||
#define SBC16(d, s) Sequence(InternalOperation(8), InternalOperation(6), {MicroOp::SBC16, &s.full, &d.full})
|
||||
|
||||
void ProcessorStorage::install_default_instruction_set() {
|
||||
MicroOp conditional_call_untaken_program[] = Sequence(ReadInc(pc_, memptr_.halves.high));
|
||||
@ -175,11 +153,8 @@ void ProcessorStorage::install_default_instruction_set() {
|
||||
assemble_base_page(fd_page_, iy_, true, fdcb_page_);
|
||||
assemble_ed_page(ed_page_);
|
||||
|
||||
fdcb_page_.r_step = 0;
|
||||
fd_page_.is_indexed = true;
|
||||
fdcb_page_.is_indexed = true;
|
||||
|
||||
ddcb_page_.r_step = 0;
|
||||
dd_page_.is_indexed = true;
|
||||
ddcb_page_.is_indexed = true;
|
||||
|
||||
@ -202,7 +177,8 @@ void ProcessorStorage::install_default_instruction_set() {
|
||||
BusOp(ReadOpcodeStart()),
|
||||
BusOp(ReadOpcodeWait(true)),
|
||||
BusOp(ReadOpcodeEnd()),
|
||||
BusOp(Refresh(6)),
|
||||
BusOp(Refresh()),
|
||||
InternalOperation(2),
|
||||
Push(pc_),
|
||||
{ MicroOp::JumpTo66, nullptr, nullptr},
|
||||
{ MicroOp::MoveToNextProgram }
|
||||
@ -212,14 +188,14 @@ void ProcessorStorage::install_default_instruction_set() {
|
||||
BusOp(IntAckStart(5, operation_)),
|
||||
BusOp(IntWait(operation_)),
|
||||
BusOp(IntAckEnd(operation_)),
|
||||
{ MicroOp::DecodeOperationNoRChange }
|
||||
{ MicroOp::DecodeOperation }
|
||||
};
|
||||
MicroOp irq_mode1_program[] = {
|
||||
{ MicroOp::BeginIRQ },
|
||||
BusOp(IntAckStart(7, operation_)), // 7 half cycles (including +
|
||||
BusOp(IntWait(operation_)), // [potentially 2 half cycles] +
|
||||
BusOp(IntAckEnd(operation_)), // Implicitly 3 half cycles +
|
||||
BusOp(Refresh(4)), // 4 half cycles +
|
||||
BusOp(Refresh()), // 4 half cycles +
|
||||
Push(pc_), // 12 half cycles = 26 half cycles = 13 cycles
|
||||
{ MicroOp::Move16, &temp16_.full, &pc_.full },
|
||||
{ MicroOp::MoveToNextProgram }
|
||||
@ -229,7 +205,7 @@ void ProcessorStorage::install_default_instruction_set() {
|
||||
BusOp(IntAckStart(7, temp16_.halves.low)),
|
||||
BusOp(IntWait(temp16_.halves.low)),
|
||||
BusOp(IntAckEnd(temp16_.halves.low)),
|
||||
BusOp(Refresh(4)),
|
||||
BusOp(Refresh()),
|
||||
Push(pc_),
|
||||
{ MicroOp::Move8, &ir_.halves.high, &temp16_.halves.high },
|
||||
Read16(temp16_, pc_),
|
||||
@ -244,8 +220,8 @@ void ProcessorStorage::install_default_instruction_set() {
|
||||
}
|
||||
|
||||
void ProcessorStorage::assemble_ed_page(InstructionPage &target) {
|
||||
#define IN_C(r) StdInstr({MicroOp::Move16, &bc_.full, &memptr_.full}, Input(bc_, r), {MicroOp::SetInFlags, &r})
|
||||
#define OUT_C(r) StdInstr(Output(bc_, r), {MicroOp::SetOutFlags})
|
||||
#define IN_C(r) Sequence({MicroOp::Move16, &bc_.full, &memptr_.full}, Input(bc_, r), {MicroOp::SetInFlags, &r})
|
||||
#define OUT_C(r) Sequence(Output(bc_, r), {MicroOp::SetOutFlags})
|
||||
#define IN_OUT(r) IN_C(r), OUT_C(r)
|
||||
|
||||
#define NOP_ROW() NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP
|
||||
@ -255,58 +231,58 @@ void ProcessorStorage::assemble_ed_page(InstructionPage &target) {
|
||||
NOP_ROW(), /* 0x20 */
|
||||
NOP_ROW(), /* 0x30 */
|
||||
/* 0x40 IN B, (C); 0x41 OUT (C), B */ IN_OUT(bc_.halves.high),
|
||||
/* 0x42 SBC HL, BC */ SBC16(hl_, bc_), /* 0x43 LD (nn), BC */ StdInstr(Read16Inc(pc_, memptr_), Write16(memptr_, bc_)),
|
||||
/* 0x44 NEG */ StdInstr({MicroOp::NEG}), /* 0x45 RETN */ StdInstr(Pop(pc_), {MicroOp::RETN}),
|
||||
/* 0x46 IM 0 */ StdInstr({MicroOp::IM}), /* 0x47 LD I, A */ Instr(6, {MicroOp::Move8, &a_, &ir_.halves.high}),
|
||||
/* 0x42 SBC HL, BC */ SBC16(hl_, bc_), /* 0x43 LD (nn), BC */ Sequence(Read16Inc(pc_, memptr_), Write16(memptr_, bc_)),
|
||||
/* 0x44 NEG */ Sequence({MicroOp::NEG}), /* 0x45 RETN */ Sequence(Pop(pc_), {MicroOp::RETN}),
|
||||
/* 0x46 IM 0 */ Sequence({MicroOp::IM}), /* 0x47 LD I, A */ Sequence(InternalOperation(2), {MicroOp::Move8, &a_, &ir_.halves.high}),
|
||||
/* 0x48 IN C, (C); 0x49 OUT (C), C */ IN_OUT(bc_.halves.low),
|
||||
/* 0x4a ADC HL, BC */ ADC16(hl_, bc_), /* 0x4b LD BC, (nn) */ StdInstr(Read16Inc(pc_, memptr_), Read16(memptr_, bc_)),
|
||||
/* 0x4c NEG */ StdInstr({MicroOp::NEG}), /* 0x4d RETI */ StdInstr(Pop(pc_), {MicroOp::RETN}),
|
||||
/* 0x4e IM 0/1 */ StdInstr({MicroOp::IM}), /* 0x4f LD R, A */ Instr(6, {MicroOp::Move8, &a_, &ir_.halves.low}),
|
||||
/* 0x4a ADC HL, BC */ ADC16(hl_, bc_), /* 0x4b LD BC, (nn) */ Sequence(Read16Inc(pc_, memptr_), Read16(memptr_, bc_)),
|
||||
/* 0x4c NEG */ Sequence({MicroOp::NEG}), /* 0x4d RETI */ Sequence(Pop(pc_), {MicroOp::RETN}),
|
||||
/* 0x4e IM 0/1 */ Sequence({MicroOp::IM}), /* 0x4f LD R, A */ Sequence(InternalOperation(2), {MicroOp::Move8, &a_, &ir_.halves.low}),
|
||||
/* 0x50 IN D, (C); 0x51 OUT (C), D */ IN_OUT(de_.halves.high),
|
||||
/* 0x52 SBC HL, DE */ SBC16(hl_, de_), /* 0x53 LD (nn), DE */ StdInstr(Read16Inc(pc_, memptr_), Write16(memptr_, de_)),
|
||||
/* 0x54 NEG */ StdInstr({MicroOp::NEG}), /* 0x55 RETN */ StdInstr(Pop(pc_), {MicroOp::RETN}),
|
||||
/* 0x56 IM 1 */ StdInstr({MicroOp::IM}), /* 0x57 LD A, I */ Instr(6, {MicroOp::Move8, &ir_.halves.high, &a_}, {MicroOp::SetAFlags}),
|
||||
/* 0x52 SBC HL, DE */ SBC16(hl_, de_), /* 0x53 LD (nn), DE */ Sequence(Read16Inc(pc_, memptr_), Write16(memptr_, de_)),
|
||||
/* 0x54 NEG */ Sequence({MicroOp::NEG}), /* 0x55 RETN */ Sequence(Pop(pc_), {MicroOp::RETN}),
|
||||
/* 0x56 IM 1 */ Sequence({MicroOp::IM}), /* 0x57 LD A, I */ Sequence(InternalOperation(2), {MicroOp::Move8, &ir_.halves.high, &a_}, {MicroOp::SetAFlags}),
|
||||
/* 0x58 IN E, (C); 0x59 OUT (C), E */ IN_OUT(de_.halves.low),
|
||||
/* 0x5a ADC HL, DE */ ADC16(hl_, de_), /* 0x5b LD DE, (nn) */ StdInstr(Read16Inc(pc_, memptr_), Read16(memptr_, de_)),
|
||||
/* 0x5c NEG */ StdInstr({MicroOp::NEG}), /* 0x5d RETN */ StdInstr(Pop(pc_), {MicroOp::RETN}),
|
||||
/* 0x5e IM 2 */ StdInstr({MicroOp::IM}), /* 0x5f LD A, R */ Instr(6, {MicroOp::Move8, &ir_.halves.low, &a_}, {MicroOp::SetAFlags}),
|
||||
/* 0x5a ADC HL, DE */ ADC16(hl_, de_), /* 0x5b LD DE, (nn) */ Sequence(Read16Inc(pc_, memptr_), Read16(memptr_, de_)),
|
||||
/* 0x5c NEG */ Sequence({MicroOp::NEG}), /* 0x5d RETN */ Sequence(Pop(pc_), {MicroOp::RETN}),
|
||||
/* 0x5e IM 2 */ Sequence({MicroOp::IM}), /* 0x5f LD A, R */ Sequence(InternalOperation(2), {MicroOp::Move8, &ir_.halves.low, &a_}, {MicroOp::SetAFlags}),
|
||||
/* 0x60 IN H, (C); 0x61 OUT (C), H */ IN_OUT(hl_.halves.high),
|
||||
/* 0x62 SBC HL, HL */ SBC16(hl_, hl_), /* 0x63 LD (nn), HL */ StdInstr(Read16Inc(pc_, memptr_), Write16(memptr_, hl_)),
|
||||
/* 0x64 NEG */ StdInstr({MicroOp::NEG}), /* 0x65 RETN */ StdInstr(Pop(pc_), {MicroOp::RETN}),
|
||||
/* 0x66 IM 0 */ StdInstr({MicroOp::IM}), /* 0x67 RRD */ StdInstr(Read3(hl_, temp8_), InternalOperation(8), {MicroOp::RRD}, Write3(hl_, temp8_)),
|
||||
/* 0x62 SBC HL, HL */ SBC16(hl_, hl_), /* 0x63 LD (nn), HL */ Sequence(Read16Inc(pc_, memptr_), Write16(memptr_, hl_)),
|
||||
/* 0x64 NEG */ Sequence({MicroOp::NEG}), /* 0x65 RETN */ Sequence(Pop(pc_), {MicroOp::RETN}),
|
||||
/* 0x66 IM 0 */ Sequence({MicroOp::IM}), /* 0x67 RRD */ Sequence(Read(hl_, temp8_), InternalOperation(8), {MicroOp::RRD}, Write(hl_, temp8_)),
|
||||
/* 0x68 IN L, (C); 0x69 OUT (C), L */ IN_OUT(hl_.halves.low),
|
||||
/* 0x6a ADC HL, HL */ ADC16(hl_, hl_), /* 0x6b LD HL, (nn) */ StdInstr(Read16Inc(pc_, memptr_), Read16(memptr_, hl_)),
|
||||
/* 0x6c NEG */ StdInstr({MicroOp::NEG}), /* 0x6d RETN */ StdInstr(Pop(pc_), {MicroOp::RETN}),
|
||||
/* 0x6e IM 0/1 */ StdInstr({MicroOp::IM}), /* 0x6f RLD */ StdInstr(Read3(hl_, temp8_), InternalOperation(8), {MicroOp::RLD}, Write3(hl_, temp8_)),
|
||||
/* 0x70 IN (C) */ IN_C(temp8_), /* 0x71 OUT (C), 0 */ StdInstr({MicroOp::SetZero}, Output(bc_, temp8_), {MicroOp::SetOutFlags}),
|
||||
/* 0x72 SBC HL, SP */ SBC16(hl_, sp_), /* 0x73 LD (nn), SP */ StdInstr(Read16Inc(pc_, memptr_), Write16(memptr_, sp_)),
|
||||
/* 0x74 NEG */ StdInstr({MicroOp::NEG}), /* 0x75 RETN */ StdInstr(Pop(pc_), {MicroOp::RETN}),
|
||||
/* 0x76 IM 1 */ StdInstr({MicroOp::IM}), /* 0x77 XX */ NOP,
|
||||
/* 0x6a ADC HL, HL */ ADC16(hl_, hl_), /* 0x6b LD HL, (nn) */ Sequence(Read16Inc(pc_, memptr_), Read16(memptr_, hl_)),
|
||||
/* 0x6c NEG */ Sequence({MicroOp::NEG}), /* 0x6d RETN */ Sequence(Pop(pc_), {MicroOp::RETN}),
|
||||
/* 0x6e IM 0/1 */ Sequence({MicroOp::IM}), /* 0x6f RLD */ Sequence(Read(hl_, temp8_), InternalOperation(8), {MicroOp::RLD}, Write(hl_, temp8_)),
|
||||
/* 0x70 IN (C) */ IN_C(temp8_), /* 0x71 OUT (C), 0 */ Sequence({MicroOp::SetZero}, Output(bc_, temp8_), {MicroOp::SetOutFlags}),
|
||||
/* 0x72 SBC HL, SP */ SBC16(hl_, sp_), /* 0x73 LD (nn), SP */ Sequence(Read16Inc(pc_, memptr_), Write16(memptr_, sp_)),
|
||||
/* 0x74 NEG */ Sequence({MicroOp::NEG}), /* 0x75 RETN */ Sequence(Pop(pc_), {MicroOp::RETN}),
|
||||
/* 0x76 IM 1 */ Sequence({MicroOp::IM}), /* 0x77 XX */ NOP,
|
||||
/* 0x78 IN A, (C); 0x79 OUT (C), A */ IN_OUT(a_),
|
||||
/* 0x7a ADC HL, SP */ ADC16(hl_, sp_), /* 0x7b LD SP, (nn) */ StdInstr(Read16Inc(pc_, memptr_), Read16(memptr_, sp_)),
|
||||
/* 0x7c NEG */ StdInstr({MicroOp::NEG}), /* 0x7d RETN */ StdInstr(Pop(pc_), {MicroOp::RETN}),
|
||||
/* 0x7e IM 2 */ StdInstr({MicroOp::IM}), /* 0x7f XX */ NOP,
|
||||
/* 0x7a ADC HL, SP */ ADC16(hl_, sp_), /* 0x7b LD SP, (nn) */ Sequence(Read16Inc(pc_, memptr_), Read16(memptr_, sp_)),
|
||||
/* 0x7c NEG */ Sequence({MicroOp::NEG}), /* 0x7d RETN */ Sequence(Pop(pc_), {MicroOp::RETN}),
|
||||
/* 0x7e IM 2 */ Sequence({MicroOp::IM}), /* 0x7f XX */ NOP,
|
||||
NOP_ROW(), /* 0x80 ... 0x8f */
|
||||
NOP_ROW(), /* 0x90 ... 0x9f */
|
||||
/* 0xa0 LDI */ StdInstr(Read3(hl_, temp8_), Write5(de_, temp8_), {MicroOp::LDI}),
|
||||
/* 0xa1 CPI */ StdInstr(Read3(hl_, temp8_), InternalOperation(10), {MicroOp::CPI}),
|
||||
/* 0xa2 INI */ Instr(6, Input(bc_, temp8_), Write3(hl_, temp8_), {MicroOp::INI}),
|
||||
/* 0xa3 OTI */ Instr(6, Read3(hl_, temp8_), {MicroOp::OUTI}, Output(bc_, temp8_)),
|
||||
/* 0xa0 LDI */ Sequence(Read(hl_, temp8_), Write(de_, temp8_), InternalOperation(4), {MicroOp::LDI}),
|
||||
/* 0xa1 CPI */ Sequence(Read(hl_, temp8_), InternalOperation(10), {MicroOp::CPI}),
|
||||
/* 0xa2 INI */ Sequence(InternalOperation(2), Input(bc_, temp8_), Write(hl_, temp8_), {MicroOp::INI}),
|
||||
/* 0xa3 OTI */ Sequence(InternalOperation(2), Read(hl_, temp8_), {MicroOp::OUTI}, Output(bc_, temp8_)),
|
||||
NOP, NOP, NOP, NOP,
|
||||
/* 0xa8 LDD */ StdInstr(Read3(hl_, temp8_), Write5(de_, temp8_), {MicroOp::LDD}),
|
||||
/* 0xa9 CPD */ StdInstr(Read3(hl_, temp8_), InternalOperation(10), {MicroOp::CPD}),
|
||||
/* 0xaa IND */ Instr(6, Input(bc_, temp8_), Write3(hl_, temp8_), {MicroOp::IND}),
|
||||
/* 0xab OTD */ Instr(6, Read3(hl_, temp8_), {MicroOp::OUTD}, Output(bc_, temp8_)),
|
||||
/* 0xa8 LDD */ Sequence(Read(hl_, temp8_), Write(de_, temp8_), InternalOperation(4), {MicroOp::LDD}),
|
||||
/* 0xa9 CPD */ Sequence(Read(hl_, temp8_), InternalOperation(10), {MicroOp::CPD}),
|
||||
/* 0xaa IND */ Sequence(InternalOperation(2), Input(bc_, temp8_), Write(hl_, temp8_), {MicroOp::IND}),
|
||||
/* 0xab OTD */ Sequence(InternalOperation(2), Read(hl_, temp8_), {MicroOp::OUTD}, Output(bc_, temp8_)),
|
||||
NOP, NOP, NOP, NOP,
|
||||
/* 0xb0 LDIR */ StdInstr(Read3(hl_, temp8_), Write5(de_, temp8_), {MicroOp::LDIR}, InternalOperation(10)),
|
||||
/* 0xb1 CPIR */ StdInstr(Read3(hl_, temp8_), InternalOperation(10), {MicroOp::CPIR}, InternalOperation(10)),
|
||||
/* 0xb2 INIR */ Instr(6, Input(bc_, temp8_), Write3(hl_, temp8_), {MicroOp::INIR}, InternalOperation(10)),
|
||||
/* 0xb3 OTIR */ Instr(6, Read3(hl_, temp8_), {MicroOp::OUTI}, Output(bc_, temp8_), {MicroOp::OUT_R}, InternalOperation(10)),
|
||||
/* 0xb0 LDIR */ Sequence(Read(hl_, temp8_), Write(de_, temp8_), InternalOperation(4), {MicroOp::LDIR}, InternalOperation(10)),
|
||||
/* 0xb1 CPIR */ Sequence(Read(hl_, temp8_), InternalOperation(10), {MicroOp::CPIR}, InternalOperation(10)),
|
||||
/* 0xb2 INIR */ Sequence(InternalOperation(2), Input(bc_, temp8_), Write(hl_, temp8_), {MicroOp::INIR}, InternalOperation(10)),
|
||||
/* 0xb3 OTIR */ Sequence(InternalOperation(2), Read(hl_, temp8_), {MicroOp::OUTI}, Output(bc_, temp8_), {MicroOp::OUT_R}, InternalOperation(10)),
|
||||
NOP, NOP, NOP, NOP,
|
||||
/* 0xb8 LDDR */ StdInstr(Read3(hl_, temp8_), Write5(de_, temp8_), {MicroOp::LDDR}, InternalOperation(10)),
|
||||
/* 0xb9 CPDR */ StdInstr(Read3(hl_, temp8_), InternalOperation(10), {MicroOp::CPDR}, InternalOperation(10)),
|
||||
/* 0xba INDR */ Instr(6, Input(bc_, temp8_), Write3(hl_, temp8_), {MicroOp::INDR}, InternalOperation(10)),
|
||||
/* 0xbb OTDR */ Instr(6, Read3(hl_, temp8_), {MicroOp::OUTD}, Output(bc_, temp8_), {MicroOp::OUT_R}, InternalOperation(10)),
|
||||
/* 0xb8 LDDR */ Sequence(Read(hl_, temp8_), Write(de_, temp8_), InternalOperation(4), {MicroOp::LDDR}, InternalOperation(10)),
|
||||
/* 0xb9 CPDR */ Sequence(Read(hl_, temp8_), InternalOperation(10), {MicroOp::CPDR}, InternalOperation(10)),
|
||||
/* 0xba INDR */ Sequence(InternalOperation(2), Input(bc_, temp8_), Write(hl_, temp8_), {MicroOp::INDR}, InternalOperation(10)),
|
||||
/* 0xbb OTDR */ Sequence(InternalOperation(2), Read(hl_, temp8_), {MicroOp::OUTD}, Output(bc_, temp8_), {MicroOp::OUT_R}, InternalOperation(10)),
|
||||
NOP, NOP, NOP, NOP,
|
||||
NOP_ROW(), /* 0xc0 */
|
||||
NOP_ROW(), /* 0xd0 */
|
||||
@ -346,77 +322,77 @@ void ProcessorStorage::assemble_cb_page(InstructionPage &target, RegisterPair16
|
||||
|
||||
void ProcessorStorage::assemble_base_page(InstructionPage &target, RegisterPair16 &index, bool add_offsets, InstructionPage &cb_page) {
|
||||
#define INC_DEC_LD(r) \
|
||||
StdInstr({MicroOp::Increment8, &r}), \
|
||||
StdInstr({MicroOp::Decrement8, &r}), \
|
||||
StdInstr(ReadInc(pc_, r))
|
||||
Sequence({MicroOp::Increment8, &r}), \
|
||||
Sequence({MicroOp::Decrement8, &r}), \
|
||||
Sequence(ReadInc(pc_, r))
|
||||
|
||||
#define INC_INC_DEC_LD(rf, r) \
|
||||
Instr(8, {MicroOp::Increment16, &rf.full}), INC_DEC_LD(r)
|
||||
Sequence(InternalOperation(4), {MicroOp::Increment16, &rf.full}), INC_DEC_LD(r)
|
||||
|
||||
#define DEC_INC_DEC_LD(rf, r) \
|
||||
Instr(8, {MicroOp::Decrement16, &rf.full}), INC_DEC_LD(r)
|
||||
Sequence(InternalOperation(4), {MicroOp::Decrement16, &rf.full}), INC_DEC_LD(r)
|
||||
|
||||
InstructionTable base_program_table = {
|
||||
/* 0x00 NOP */ NOP, /* 0x01 LD BC, nn */ StdInstr(Read16Inc(pc_, bc_)),
|
||||
/* 0x02 LD (BC), A */ StdInstr({MicroOp::SetAddrAMemptr, &bc_.full}, Write3(bc_, a_)),
|
||||
/* 0x00 NOP */ NOP, /* 0x01 LD BC, nn */ Sequence(Read16Inc(pc_, bc_)),
|
||||
/* 0x02 LD (BC), A */ Sequence({MicroOp::SetAddrAMemptr, &bc_.full}, Write(bc_, a_)),
|
||||
|
||||
/* 0x03 INC BC; 0x04 INC B; 0x05 DEC B; 0x06 LD B, n */
|
||||
INC_INC_DEC_LD(bc_, bc_.halves.high),
|
||||
|
||||
/* 0x07 RLCA */ StdInstr({MicroOp::RLCA}),
|
||||
/* 0x08 EX AF, AF' */ StdInstr({MicroOp::ExAFAFDash}), /* 0x09 ADD HL, BC */ ADD16(index, bc_),
|
||||
/* 0x0a LD A, (BC) */ StdInstr({MicroOp::Move16, &bc_.full, &memptr_.full}, Read3(memptr_, a_), Inc16(memptr_)),
|
||||
/* 0x07 RLCA */ Sequence({MicroOp::RLCA}),
|
||||
/* 0x08 EX AF, AF' */ Sequence({MicroOp::ExAFAFDash}), /* 0x09 ADD HL, BC */ ADD16(index, bc_),
|
||||
/* 0x0a LD A, (BC) */ Sequence({MicroOp::Move16, &bc_.full, &memptr_.full}, Read(memptr_, a_), Inc16(memptr_)),
|
||||
|
||||
/* 0x0b DEC BC; 0x0c INC C; 0x0d DEC C; 0x0e LD C, n */
|
||||
DEC_INC_DEC_LD(bc_, bc_.halves.low),
|
||||
|
||||
/* 0x0f RRCA */ StdInstr({MicroOp::RRCA}),
|
||||
/* 0x10 DJNZ */ Instr(6, ReadInc(pc_, temp8_), {MicroOp::DJNZ}, InternalOperation(10), {MicroOp::CalculateIndexAddress, &pc_.full}, {MicroOp::Move16, &memptr_.full, &pc_.full}),
|
||||
/* 0x11 LD DE, nn */ StdInstr(Read16Inc(pc_, de_)),
|
||||
/* 0x12 LD (DE), A */ StdInstr({MicroOp::SetAddrAMemptr, &de_.full}, Write3(de_, a_)),
|
||||
/* 0x0f RRCA */ Sequence({MicroOp::RRCA}),
|
||||
/* 0x10 DJNZ */ Sequence(InternalOperation(2), ReadInc(pc_, temp8_), {MicroOp::DJNZ}, InternalOperation(10), {MicroOp::CalculateIndexAddress, &pc_.full}, {MicroOp::Move16, &memptr_.full, &pc_.full}),
|
||||
/* 0x11 LD DE, nn */ Sequence(Read16Inc(pc_, de_)),
|
||||
/* 0x12 LD (DE), A */ Sequence({MicroOp::SetAddrAMemptr, &de_.full}, Write(de_, a_)),
|
||||
|
||||
/* 0x13 INC DE; 0x14 INC D; 0x15 DEC D; 0x16 LD D, n */
|
||||
INC_INC_DEC_LD(de_, de_.halves.high),
|
||||
|
||||
/* 0x17 RLA */ StdInstr({MicroOp::RLA}),
|
||||
/* 0x18 JR */ StdInstr(ReadInc(pc_, temp8_), InternalOperation(10), {MicroOp::CalculateIndexAddress, &pc_.full}, {MicroOp::Move16, &memptr_.full, &pc_.full}),
|
||||
/* 0x17 RLA */ Sequence({MicroOp::RLA}),
|
||||
/* 0x18 JR */ Sequence(ReadInc(pc_, temp8_), InternalOperation(10), {MicroOp::CalculateIndexAddress, &pc_.full}, {MicroOp::Move16, &memptr_.full, &pc_.full}),
|
||||
/* 0x19 ADD HL, DE */ ADD16(index, de_),
|
||||
/* 0x1a LD A, (DE) */ StdInstr({MicroOp::Move16, &de_.full, &memptr_.full}, Read3(memptr_, a_), Inc16(memptr_)),
|
||||
/* 0x1a LD A, (DE) */ Sequence({MicroOp::Move16, &de_.full, &memptr_.full}, Read(memptr_, a_), Inc16(memptr_)),
|
||||
|
||||
/* 0x1b DEC DE; 0x1c INC E; 0x1d DEC E; 0x1e LD E, n */
|
||||
DEC_INC_DEC_LD(de_, de_.halves.low),
|
||||
|
||||
/* 0x1f RRA */ StdInstr({MicroOp::RRA}),
|
||||
/* 0x20 JR NZ */ JR(TestNZ), /* 0x21 LD HL, nn */ StdInstr(Read16Inc(pc_, index)),
|
||||
/* 0x22 LD (nn), HL */ StdInstr(Read16Inc(pc_, memptr_), Write16(memptr_, index)),
|
||||
/* 0x1f RRA */ Sequence({MicroOp::RRA}),
|
||||
/* 0x20 JR NZ */ JR(TestNZ), /* 0x21 LD HL, nn */ Sequence(Read16Inc(pc_, index)),
|
||||
/* 0x22 LD (nn), HL */ Sequence(Read16Inc(pc_, memptr_), Write16(memptr_, index)),
|
||||
|
||||
/* 0x23 INC HL; 0x24 INC H; 0x25 DEC H; 0x26 LD H, n */
|
||||
INC_INC_DEC_LD(index, index.halves.high),
|
||||
|
||||
/* 0x27 DAA */ StdInstr({MicroOp::DAA}),
|
||||
/* 0x27 DAA */ Sequence({MicroOp::DAA}),
|
||||
/* 0x28 JR Z */ JR(TestZ), /* 0x29 ADD HL, HL */ ADD16(index, index),
|
||||
/* 0x2a LD HL, (nn) */ StdInstr(Read16Inc(pc_, memptr_), Read16(memptr_, index)),
|
||||
/* 0x2a LD HL, (nn) */ Sequence(Read16Inc(pc_, memptr_), Read16(memptr_, index)),
|
||||
|
||||
/* 0x2b DEC HL; 0x2c INC L; 0x2d DEC L; 0x2e LD L, n */
|
||||
DEC_INC_DEC_LD(index, index.halves.low),
|
||||
|
||||
/* 0x2f CPL */ StdInstr({MicroOp::CPL}),
|
||||
/* 0x30 JR NC */ JR(TestNC), /* 0x31 LD SP, nn */ StdInstr(Read16Inc(pc_, sp_)),
|
||||
/* 0x32 LD (nn), A */ StdInstr(Read16Inc(pc_, temp16_), {MicroOp::SetAddrAMemptr, &temp16_.full}, Write3(temp16_, a_)),
|
||||
/* 0x33 INC SP */ Instr(8, {MicroOp::Increment16, &sp_.full}),
|
||||
/* 0x34 INC (HL) */ StdInstr(INDEX(), Read4Pre(INDEX_ADDR(), temp8_), {MicroOp::Increment8, &temp8_}, Write3(INDEX_ADDR(), temp8_)),
|
||||
/* 0x35 DEC (HL) */ StdInstr(INDEX(), Read4Pre(INDEX_ADDR(), temp8_), {MicroOp::Decrement8, &temp8_}, Write3(INDEX_ADDR(), temp8_)),
|
||||
/* 0x36 LD (HL), n */ StdInstr(ReadInc(pc_, temp8_), Write3(INDEX_ADDR(), temp8_)),
|
||||
/* 0x37 SCF */ StdInstr({MicroOp::SCF}),
|
||||
/* 0x2f CPL */ Sequence({MicroOp::CPL}),
|
||||
/* 0x30 JR NC */ JR(TestNC), /* 0x31 LD SP, nn */ Sequence(Read16Inc(pc_, sp_)),
|
||||
/* 0x32 LD (nn), A */ Sequence(Read16Inc(pc_, temp16_), {MicroOp::SetAddrAMemptr, &temp16_.full}, Write(temp16_, a_)),
|
||||
/* 0x33 INC SP */ Sequence(InternalOperation(4), {MicroOp::Increment16, &sp_.full}),
|
||||
/* 0x34 INC (HL) */ Sequence(INDEX(), Read(INDEX_ADDR(), temp8_), InternalOperation(2), {MicroOp::Increment8, &temp8_}, Write(INDEX_ADDR(), temp8_)),
|
||||
/* 0x35 DEC (HL) */ Sequence(INDEX(), Read(INDEX_ADDR(), temp8_), InternalOperation(2), {MicroOp::Decrement8, &temp8_}, Write(INDEX_ADDR(), temp8_)),
|
||||
/* 0x36 LD (HL), n */ Sequence(ReadInc(pc_, temp8_), Write(INDEX_ADDR(), temp8_)),
|
||||
/* 0x37 SCF */ Sequence({MicroOp::SCF}),
|
||||
/* 0x38 JR C */ JR(TestC),
|
||||
/* 0x39 ADD HL, SP */ ADD16(index, sp_),
|
||||
/* 0x3a LD A, (nn) */ StdInstr(Read16Inc(pc_, memptr_), Read3(memptr_, a_), Inc16(memptr_)),
|
||||
/* 0x3b DEC SP */ Instr(8, {MicroOp::Decrement16, &sp_.full}),
|
||||
/* 0x3a LD A, (nn) */ Sequence(Read16Inc(pc_, memptr_), Read(memptr_, a_), Inc16(memptr_)),
|
||||
/* 0x3b DEC SP */ Sequence(InternalOperation(4), {MicroOp::Decrement16, &sp_.full}),
|
||||
|
||||
/* 0x3c INC A; 0x3d DEC A; 0x3e LD A, n */
|
||||
INC_DEC_LD(a_),
|
||||
|
||||
/* 0x3f CCF */ StdInstr({MicroOp::CCF}),
|
||||
/* 0x3f CCF */ Sequence({MicroOp::CCF}),
|
||||
|
||||
/* 0x40 LD B, B; 0x41 LD B, C; 0x42 LD B, D; 0x43 LD B, E; 0x44 LD B, H; 0x45 LD B, L; 0x46 LD B, (HL); 0x47 LD B, A */
|
||||
LD_GROUP(bc_.halves.high, bc_.halves.high),
|
||||
@ -436,14 +412,14 @@ void ProcessorStorage::assemble_base_page(InstructionPage &target, RegisterPair1
|
||||
/* 0x68 LD L, B; 0x69 LD L, C; 0x6a LD L, D; 0x6b LD L, E; 0x6c LD L, H; 0x6d LD H, L; 0x6e LD L, (HL); 0x6f LD L, A */
|
||||
LD_GROUP(index.halves.low, hl_.halves.low),
|
||||
|
||||
/* 0x70 LD (HL), B */ StdInstr(INDEX(), Write3(INDEX_ADDR(), bc_.halves.high)),
|
||||
/* 0x71 LD (HL), C */ StdInstr(INDEX(), Write3(INDEX_ADDR(), bc_.halves.low)),
|
||||
/* 0x72 LD (HL), D */ StdInstr(INDEX(), Write3(INDEX_ADDR(), de_.halves.high)),
|
||||
/* 0x73 LD (HL), E */ StdInstr(INDEX(), Write3(INDEX_ADDR(), de_.halves.low)),
|
||||
/* 0x74 LD (HL), H */ StdInstr(INDEX(), Write3(INDEX_ADDR(), hl_.halves.high)), // neither of these stores parts of the index register;
|
||||
/* 0x75 LD (HL), L */ StdInstr(INDEX(), Write3(INDEX_ADDR(), hl_.halves.low)), // they always store exactly H and L.
|
||||
/* 0x76 HALT */ StdInstr({MicroOp::HALT}),
|
||||
/* 0x77 LD (HL), A */ StdInstr(INDEX(), Write3(INDEX_ADDR(), a_)),
|
||||
/* 0x70 LD (HL), B */ Sequence(INDEX(), Write(INDEX_ADDR(), bc_.halves.high)),
|
||||
/* 0x71 LD (HL), C */ Sequence(INDEX(), Write(INDEX_ADDR(), bc_.halves.low)),
|
||||
/* 0x72 LD (HL), D */ Sequence(INDEX(), Write(INDEX_ADDR(), de_.halves.high)),
|
||||
/* 0x73 LD (HL), E */ Sequence(INDEX(), Write(INDEX_ADDR(), de_.halves.low)),
|
||||
/* 0x74 LD (HL), H */ Sequence(INDEX(), Write(INDEX_ADDR(), hl_.halves.high)), // neither of these stores parts of the index register;
|
||||
/* 0x75 LD (HL), L */ Sequence(INDEX(), Write(INDEX_ADDR(), hl_.halves.low)), // they always store exactly H and L.
|
||||
/* 0x76 HALT */ Sequence({MicroOp::HALT}),
|
||||
/* 0x77 LD (HL), A */ Sequence(INDEX(), Write(INDEX_ADDR(), a_)),
|
||||
|
||||
/* 0x78 LD A, B; 0x79 LD A, C; 0x7a LD A, D; 0x7b LD A, E; 0x7c LD A, H; 0x7d LD A, L; 0x7e LD A, (HL); 0x7f LD A, A */
|
||||
LD_GROUP(a_, a_),
|
||||
@ -472,45 +448,45 @@ void ProcessorStorage::assemble_base_page(InstructionPage &target, RegisterPair1
|
||||
/* 0xb8 CP B; 0xb9 CP C; 0xba CP D; 0xbb CP E; 0xbc CP H; 0xbd CP L; 0xbe CP (HL); 0xbf CP A */
|
||||
READ_OP_GROUP(CP8),
|
||||
|
||||
/* 0xc0 RET NZ */ RET(TestNZ), /* 0xc1 POP BC */ StdInstr(Pop(bc_)),
|
||||
/* 0xc2 JP NZ */ JP(TestNZ), /* 0xc3 JP nn */ StdInstr(Read16(pc_, memptr_), {MicroOp::Move16, &memptr_.full, &pc_.full}),
|
||||
/* 0xc4 CALL NZ */ CALL(TestNZ), /* 0xc5 PUSH BC */ Instr(6, Push(bc_)),
|
||||
/* 0xc6 ADD A, n */ StdInstr(ReadInc(pc_, temp8_), {MicroOp::ADD8, &temp8_}),
|
||||
/* 0xc0 RET NZ */ RET(TestNZ), /* 0xc1 POP BC */ Sequence(Pop(bc_)),
|
||||
/* 0xc2 JP NZ */ JP(TestNZ), /* 0xc3 JP nn */ Sequence(Read16(pc_, memptr_), {MicroOp::Move16, &memptr_.full, &pc_.full}),
|
||||
/* 0xc4 CALL NZ */ CALL(TestNZ), /* 0xc5 PUSH BC */ Sequence(InternalOperation(2), Push(bc_)),
|
||||
/* 0xc6 ADD A, n */ Sequence(ReadInc(pc_, temp8_), {MicroOp::ADD8, &temp8_}),
|
||||
/* 0xc7 RST 00h */ RST(),
|
||||
/* 0xc8 RET Z */ RET(TestZ), /* 0xc9 RET */ StdInstr(Pop(memptr_), {MicroOp::Move16, &memptr_.full, &pc_.full}),
|
||||
/* 0xca JP Z */ JP(TestZ), /* 0xcb [CB page] */StdInstr(FINDEX(), {MicroOp::SetInstructionPage, &cb_page}),
|
||||
/* 0xcc CALL Z */ CALL(TestZ), /* 0xcd CALL */ StdInstr(ReadInc(pc_, memptr_.halves.low), Read4Inc(pc_, memptr_.halves.high), Push(pc_), {MicroOp::Move16, &memptr_.full, &pc_.full}),
|
||||
/* 0xce ADC A, n */ StdInstr(ReadInc(pc_, temp8_), {MicroOp::ADC8, &temp8_}),
|
||||
/* 0xc8 RET Z */ RET(TestZ), /* 0xc9 RET */ Sequence(Pop(memptr_), {MicroOp::Move16, &memptr_.full, &pc_.full}),
|
||||
/* 0xca JP Z */ JP(TestZ), /* 0xcb [CB page] */Sequence(FINDEX(), {MicroOp::SetInstructionPage, &cb_page}),
|
||||
/* 0xcc CALL Z */ CALL(TestZ), /* 0xcd CALL */ Sequence(ReadInc(pc_, memptr_.halves.low), ReadInc(pc_, memptr_.halves.high), InternalOperation(2), Push(pc_), {MicroOp::Move16, &memptr_.full, &pc_.full}),
|
||||
/* 0xce ADC A, n */ Sequence(ReadInc(pc_, temp8_), {MicroOp::ADC8, &temp8_}),
|
||||
/* 0xcf RST 08h */ RST(),
|
||||
/* 0xd0 RET NC */ RET(TestNC), /* 0xd1 POP DE */ StdInstr(Pop(de_)),
|
||||
/* 0xd2 JP NC */ JP(TestNC), /* 0xd3 OUT (n), A */StdInstr(ReadInc(pc_, memptr_.halves.low), {MicroOp::Move8, &a_, &memptr_.halves.high}, Output(memptr_, a_), Inc8NoFlags(memptr_.halves.low)),
|
||||
/* 0xd4 CALL NC */ CALL(TestNC), /* 0xd5 PUSH DE */ Instr(6, Push(de_)),
|
||||
/* 0xd6 SUB n */ StdInstr(ReadInc(pc_, temp8_), {MicroOp::SUB8, &temp8_}),
|
||||
/* 0xd0 RET NC */ RET(TestNC), /* 0xd1 POP DE */ Sequence(Pop(de_)),
|
||||
/* 0xd2 JP NC */ JP(TestNC), /* 0xd3 OUT (n), A */Sequence(ReadInc(pc_, memptr_.halves.low), {MicroOp::Move8, &a_, &memptr_.halves.high}, Output(memptr_, a_), Inc8NoFlags(memptr_.halves.low)),
|
||||
/* 0xd4 CALL NC */ CALL(TestNC), /* 0xd5 PUSH DE */ Sequence(InternalOperation(2), Push(de_)),
|
||||
/* 0xd6 SUB n */ Sequence(ReadInc(pc_, temp8_), {MicroOp::SUB8, &temp8_}),
|
||||
/* 0xd7 RST 10h */ RST(),
|
||||
/* 0xd8 RET C */ RET(TestC), /* 0xd9 EXX */ StdInstr({MicroOp::EXX}),
|
||||
/* 0xda JP C */ JP(TestC), /* 0xdb IN A, (n) */StdInstr(ReadInc(pc_, memptr_.halves.low), {MicroOp::Move8, &a_, &memptr_.halves.high}, Input(memptr_, a_), Inc16(memptr_)),
|
||||
/* 0xdc CALL C */ CALL(TestC), /* 0xdd [DD page] */StdInstr({MicroOp::SetInstructionPage, &dd_page_}),
|
||||
/* 0xde SBC A, n */ StdInstr(ReadInc(pc_, temp8_), {MicroOp::SBC8, &temp8_}),
|
||||
/* 0xd8 RET C */ RET(TestC), /* 0xd9 EXX */ Sequence({MicroOp::EXX}),
|
||||
/* 0xda JP C */ JP(TestC), /* 0xdb IN A, (n) */Sequence(ReadInc(pc_, memptr_.halves.low), {MicroOp::Move8, &a_, &memptr_.halves.high}, Input(memptr_, a_), Inc16(memptr_)),
|
||||
/* 0xdc CALL C */ CALL(TestC), /* 0xdd [DD page] */Sequence({MicroOp::SetInstructionPage, &dd_page_}),
|
||||
/* 0xde SBC A, n */ Sequence(ReadInc(pc_, temp8_), {MicroOp::SBC8, &temp8_}),
|
||||
/* 0xdf RST 18h */ RST(),
|
||||
/* 0xe0 RET PO */ RET(TestPO), /* 0xe1 POP HL */ StdInstr(Pop(index)),
|
||||
/* 0xe2 JP PO */ JP(TestPO), /* 0xe3 EX (SP), HL */StdInstr(Pop7(memptr_), Push8(index), {MicroOp::Move16, &memptr_.full, &index.full}),
|
||||
/* 0xe4 CALL PO */ CALL(TestPO), /* 0xe5 PUSH HL */ Instr(6, Push(index)),
|
||||
/* 0xe6 AND n */ StdInstr(ReadInc(pc_, temp8_), {MicroOp::And, &temp8_}),
|
||||
/* 0xe0 RET PO */ RET(TestPO), /* 0xe1 POP HL */ Sequence(Pop(index)),
|
||||
/* 0xe2 JP PO */ JP(TestPO), /* 0xe3 EX (SP), HL */Sequence(Pop(memptr_), InternalOperation(2), Push(index), InternalOperation(4), {MicroOp::Move16, &memptr_.full, &index.full}),
|
||||
/* 0xe4 CALL PO */ CALL(TestPO), /* 0xe5 PUSH HL */ Sequence(InternalOperation(2), Push(index)),
|
||||
/* 0xe6 AND n */ Sequence(ReadInc(pc_, temp8_), {MicroOp::And, &temp8_}),
|
||||
/* 0xe7 RST 20h */ RST(),
|
||||
/* 0xe8 RET PE */ RET(TestPE), /* 0xe9 JP (HL) */ StdInstr({MicroOp::Move16, &index.full, &pc_.full}),
|
||||
/* 0xea JP PE */ JP(TestPE), /* 0xeb EX DE, HL */StdInstr({MicroOp::ExDEHL}),
|
||||
/* 0xec CALL PE */ CALL(TestPE), /* 0xed [ED page] */StdInstr({MicroOp::SetInstructionPage, &ed_page_}),
|
||||
/* 0xee XOR n */ StdInstr(ReadInc(pc_, temp8_), {MicroOp::Xor, &temp8_}),
|
||||
/* 0xe8 RET PE */ RET(TestPE), /* 0xe9 JP (HL) */ Sequence({MicroOp::Move16, &index.full, &pc_.full}),
|
||||
/* 0xea JP PE */ JP(TestPE), /* 0xeb EX DE, HL */Sequence({MicroOp::ExDEHL}),
|
||||
/* 0xec CALL PE */ CALL(TestPE), /* 0xed [ED page] */Sequence({MicroOp::SetInstructionPage, &ed_page_}),
|
||||
/* 0xee XOR n */ Sequence(ReadInc(pc_, temp8_), {MicroOp::Xor, &temp8_}),
|
||||
/* 0xef RST 28h */ RST(),
|
||||
/* 0xf0 RET p */ RET(TestP), /* 0xf1 POP AF */ StdInstr(Pop(temp16_), {MicroOp::DisassembleAF}),
|
||||
/* 0xf2 JP P */ JP(TestP), /* 0xf3 DI */ StdInstr({MicroOp::DI}),
|
||||
/* 0xf4 CALL P */ CALL(TestP), /* 0xf5 PUSH AF */ Instr(6, {MicroOp::AssembleAF}, Push(temp16_)),
|
||||
/* 0xf6 OR n */ StdInstr(ReadInc(pc_, temp8_), {MicroOp::Or, &temp8_}),
|
||||
/* 0xf0 RET p */ RET(TestP), /* 0xf1 POP AF */ Sequence(Pop(temp16_), {MicroOp::DisassembleAF}),
|
||||
/* 0xf2 JP P */ JP(TestP), /* 0xf3 DI */ Sequence({MicroOp::DI}),
|
||||
/* 0xf4 CALL P */ CALL(TestP), /* 0xf5 PUSH AF */ Sequence(InternalOperation(2), {MicroOp::AssembleAF}, Push(temp16_)),
|
||||
/* 0xf6 OR n */ Sequence(ReadInc(pc_, temp8_), {MicroOp::Or, &temp8_}),
|
||||
/* 0xf7 RST 30h */ RST(),
|
||||
/* 0xf8 RET M */ RET(TestM), /* 0xf9 LD SP, HL */Instr(8, {MicroOp::Move16, &index.full, &sp_.full}),
|
||||
/* 0xfa JP M */ JP(TestM), /* 0xfb EI */ StdInstr({MicroOp::EI}),
|
||||
/* 0xfc CALL M */ CALL(TestM), /* 0xfd [FD page] */StdInstr({MicroOp::SetInstructionPage, &fd_page_}),
|
||||
/* 0xfe CP n */ StdInstr(ReadInc(pc_, temp8_), {MicroOp::CP8, &temp8_}),
|
||||
/* 0xf8 RET M */ RET(TestM), /* 0xf9 LD SP, HL */Sequence(InternalOperation(4), {MicroOp::Move16, &index.full, &sp_.full}),
|
||||
/* 0xfa JP M */ JP(TestM), /* 0xfb EI */ Sequence({MicroOp::EI}),
|
||||
/* 0xfc CALL M */ CALL(TestM), /* 0xfd [FD page] */Sequence({MicroOp::SetInstructionPage, &fd_page_}),
|
||||
/* 0xfe CP n */ Sequence(ReadInc(pc_, temp8_), {MicroOp::CP8, &temp8_}),
|
||||
/* 0xff RST 38h */ RST(),
|
||||
};
|
||||
|
||||
@ -518,7 +494,7 @@ void ProcessorStorage::assemble_base_page(InstructionPage &target, RegisterPair1
|
||||
// The indexed version of 0x36 differs substantially from the non-indexed by building index calculation into
|
||||
// the cycle that fetches the final operand. So patch in a different microprogram if building an indexed table.
|
||||
InstructionTable copy_table = {
|
||||
StdInstr(FINDEX(), Read5Inc(pc_, temp8_), Write3(INDEX_ADDR(), temp8_))
|
||||
Sequence(FINDEX(), ReadInc(pc_, temp8_), InternalOperation(4), Write(INDEX_ADDR(), temp8_))
|
||||
};
|
||||
std::memcpy(&base_program_table[0x36], ©_table[0], sizeof(copy_table[0]));
|
||||
}
|
||||
@ -528,19 +504,27 @@ void ProcessorStorage::assemble_base_page(InstructionPage &target, RegisterPair1
|
||||
}
|
||||
|
||||
void ProcessorStorage::assemble_fetch_decode_execute(InstructionPage &target, int length) {
|
||||
/// The fetch-decode-execute sequence for a regular four-clock M1 cycle.
|
||||
const MicroOp normal_fetch_decode_execute[] = {
|
||||
BusOp(ReadOpcodeStart()),
|
||||
BusOp(ReadOpcodeWait(true)),
|
||||
BusOp(ReadOpcodeEnd()),
|
||||
{ MicroOp::IncrementR },
|
||||
BusOp(Refresh()),
|
||||
{ MicroOp::DecodeOperation }
|
||||
};
|
||||
|
||||
/// The concluding fetch-decode-execute of a [dd/fd]cb nn oo sequence, i.e. an (IX+n) or (IY+n) operation.
|
||||
/// Per the observed 48kb/128kb Spectrum timings, this appears not to include a refresh cycle. So I've also
|
||||
/// taken a punt on it not incrementing R.
|
||||
const MicroOp short_fetch_decode_execute[] = {
|
||||
BusOp(ReadOpcodeStart()),
|
||||
BusOp(ReadOpcodeWait(false)),
|
||||
BusOp(ReadOpcodeWait(true)),
|
||||
BusOp(ReadOpcodeEnd()),
|
||||
{ MicroOp::DecodeOperation }
|
||||
BusOp(ReadStart(pc_, operation_)),
|
||||
BusOp(ReadWait(pc_, operation_)),
|
||||
BusOp(ReadEnd(pc_, operation_)),
|
||||
InternalOperation(4),
|
||||
{ MicroOp::DecodeOperation },
|
||||
};
|
||||
|
||||
copy_program((length == 4) ? normal_fetch_decode_execute : short_fetch_decode_execute, target.fetch_decode_execute);
|
||||
target.fetch_decode_execute_data = target.fetch_decode_execute.data();
|
||||
}
|
||||
|
||||
@ -16,8 +16,8 @@ class ProcessorStorage {
|
||||
struct MicroOp {
|
||||
enum Type {
|
||||
BusOperation,
|
||||
IncrementR,
|
||||
DecodeOperation,
|
||||
DecodeOperationNoRChange,
|
||||
MoveToNextProgram,
|
||||
|
||||
Increment8NoFlags,
|
||||
@ -121,7 +121,6 @@ class ProcessorStorage {
|
||||
std::vector<MicroOp> all_operations;
|
||||
std::vector<MicroOp> fetch_decode_execute;
|
||||
MicroOp *fetch_decode_execute_data = nullptr;
|
||||
uint8_t r_step = 1;
|
||||
bool is_indexed = false;
|
||||
};
|
||||
|
||||
@ -149,6 +148,8 @@ class ProcessorStorage {
|
||||
// that knowledge of what the last opcode did is necessary to get bits 5 & 3
|
||||
// correct for SCF and CCF.
|
||||
|
||||
uint16_t last_address_bus_ = 0; // The value most recently put out on the address bus.
|
||||
|
||||
HalfCycles number_of_cycles_;
|
||||
|
||||
enum Interrupt: uint8_t {
|
||||
|
||||
@ -68,29 +68,50 @@ enum Flag: uint8_t {
|
||||
*/
|
||||
struct PartialMachineCycle {
|
||||
enum Operation {
|
||||
/// The final half cycle of the opcode fetch part of an M1 cycle.
|
||||
ReadOpcode = 0,
|
||||
/// The 1.5 cycles of a read cycle.
|
||||
Read,
|
||||
/// The 1.5 cycles of a write cycle.
|
||||
Write,
|
||||
/// The 1.5 cycles of an input cycle.
|
||||
Input,
|
||||
/// The 1.5 cycles of an output cycle.
|
||||
Output,
|
||||
/// The 1.5 cycles of an interrupt acknowledgment.
|
||||
Interrupt,
|
||||
|
||||
/// The two-cycle refresh part of an M1 cycle.
|
||||
Refresh,
|
||||
/// A period with no changes in bus signalling.
|
||||
Internal,
|
||||
/// A bus acknowledgement cycle.
|
||||
BusAcknowledge,
|
||||
|
||||
/// A wait state within an M1 cycle.
|
||||
ReadOpcodeWait,
|
||||
/// A wait state within a read cycle.
|
||||
ReadWait,
|
||||
/// A wait state within a write cycle.
|
||||
WriteWait,
|
||||
/// A wait state within an input cycle.
|
||||
InputWait,
|
||||
/// A wait state within an output cycle.
|
||||
OutputWait,
|
||||
/// A wait state within an interrupt acknowledge cycle.
|
||||
InterruptWait,
|
||||
|
||||
/// The first 1.5 cycles of an M1 bus cycle, up to the sampling of WAIT.
|
||||
ReadOpcodeStart,
|
||||
/// The first 1.5 cycles of a read cycle, up to the sampling of WAIT.
|
||||
ReadStart,
|
||||
/// The first 1.5 cycles of a write cycle, up to the sampling of WAIT.
|
||||
WriteStart,
|
||||
/// The first 1.5 samples of an input bus cycle, up to the sampling of WAIT.
|
||||
InputStart,
|
||||
/// The first 1.5 samples of an output bus cycle, up to the sampling of WAIT.
|
||||
OutputStart,
|
||||
/// The first portion of an interrupt acknowledgement — 2.5 or 3.5 cycles, depending on interrupt mode.
|
||||
InterruptStart,
|
||||
};
|
||||
/// The operation being carried out by the Z80. See the various getters below for better classification.
|
||||
@ -125,6 +146,230 @@ struct PartialMachineCycle {
|
||||
return operation >= Operation::ReadOpcodeWait && operation <= Operation::InterruptWait;
|
||||
}
|
||||
|
||||
enum Line {
|
||||
CLK = 1 << 0,
|
||||
|
||||
MREQ = 1 << 1,
|
||||
IOREQ = 1 << 2,
|
||||
|
||||
RD = 1 << 3,
|
||||
WR = 1 << 4,
|
||||
RFSH = 1 << 5,
|
||||
|
||||
M1 = 1 << 6,
|
||||
|
||||
BUSACK = 1 << 7,
|
||||
};
|
||||
|
||||
/// @returns A C-style array of the bus state at the beginning of each half cycle in this
|
||||
/// partial machine cycle. Each element is a combination of bit masks from the Line enum;
|
||||
/// bit set means line active, bit clear means line inactive. For the CLK line set means high.
|
||||
///
|
||||
/// @discussion This discrete sampling is prone to aliasing errors. Beware.
|
||||
const uint8_t *bus_state() const {
|
||||
switch(operation) {
|
||||
|
||||
//
|
||||
// M1 cycle
|
||||
//
|
||||
|
||||
case Operation::ReadOpcodeStart: {
|
||||
static constexpr uint8_t states[] = {
|
||||
Line::CLK | Line::M1,
|
||||
Line::M1 | Line::MREQ | Line::RD,
|
||||
Line::CLK | Line::M1 | Line::MREQ | Line::RD,
|
||||
};
|
||||
return states;
|
||||
}
|
||||
|
||||
case Operation::ReadOpcode:
|
||||
case Operation::ReadOpcodeWait: {
|
||||
static constexpr uint8_t states[] = {
|
||||
Line::M1 | Line::MREQ | Line::RD,
|
||||
Line::CLK | Line::M1 | Line::MREQ | Line::RD,
|
||||
};
|
||||
return states;
|
||||
}
|
||||
|
||||
case Operation::Refresh: {
|
||||
static constexpr uint8_t states[] = {
|
||||
Line::CLK | Line::RFSH | Line::MREQ,
|
||||
Line::RFSH,
|
||||
Line::CLK | Line::RFSH | Line::MREQ,
|
||||
Line::RFSH | Line::MREQ,
|
||||
Line::CLK | Line::RFSH,
|
||||
Line::RFSH,
|
||||
Line::CLK | Line::RFSH,
|
||||
Line::RFSH,
|
||||
};
|
||||
return states;
|
||||
}
|
||||
|
||||
//
|
||||
// Read cycle.
|
||||
//
|
||||
|
||||
case Operation::ReadStart: {
|
||||
static constexpr uint8_t states[] = {
|
||||
Line::CLK,
|
||||
Line::RD | Line::MREQ,
|
||||
Line::CLK | Line::RD | Line::MREQ,
|
||||
};
|
||||
return states;
|
||||
}
|
||||
|
||||
case Operation::ReadWait: {
|
||||
static constexpr uint8_t states[] = {
|
||||
Line::MREQ | Line::RD,
|
||||
Line::CLK | Line::MREQ | Line::RD,
|
||||
Line::MREQ | Line::RD,
|
||||
Line::CLK | Line::MREQ | Line::RD,
|
||||
Line::MREQ | Line::RD,
|
||||
Line::CLK | Line::MREQ | Line::RD,
|
||||
};
|
||||
return states;
|
||||
}
|
||||
|
||||
case Operation::Read: {
|
||||
static constexpr uint8_t states[] = {
|
||||
Line::MREQ | Line::RD,
|
||||
Line::CLK | Line::MREQ | Line::RD,
|
||||
0,
|
||||
};
|
||||
return states;
|
||||
}
|
||||
|
||||
//
|
||||
// Write cycle.
|
||||
//
|
||||
|
||||
case Operation::WriteStart: {
|
||||
static constexpr uint8_t states[] = {
|
||||
Line::CLK,
|
||||
Line::MREQ,
|
||||
Line::CLK | Line::MREQ,
|
||||
};
|
||||
return states;
|
||||
}
|
||||
|
||||
case Operation::WriteWait: {
|
||||
static constexpr uint8_t states[] = {
|
||||
Line::MREQ,
|
||||
Line::CLK | Line::MREQ,
|
||||
Line::MREQ,
|
||||
Line::CLK | Line::MREQ,
|
||||
Line::MREQ,
|
||||
Line::CLK | Line::MREQ,
|
||||
};
|
||||
return states;
|
||||
}
|
||||
|
||||
case Operation::Write: {
|
||||
static constexpr uint8_t states[] = {
|
||||
Line::MREQ | Line::WR,
|
||||
Line::CLK | Line::MREQ | Line::WR,
|
||||
0,
|
||||
};
|
||||
return states;
|
||||
}
|
||||
|
||||
//
|
||||
// Input cycle.
|
||||
//
|
||||
|
||||
case Operation::InputStart: {
|
||||
static constexpr uint8_t states[] = {
|
||||
Line::CLK,
|
||||
0,
|
||||
Line::CLK | Line::IOREQ | Line::RD,
|
||||
};
|
||||
return states;
|
||||
}
|
||||
|
||||
case Operation::InputWait: {
|
||||
static constexpr uint8_t states[] = {
|
||||
Line::IOREQ | Line::RD,
|
||||
Line::CLK | Line::IOREQ | Line::RD,
|
||||
};
|
||||
return states;
|
||||
}
|
||||
|
||||
case Operation::Input: {
|
||||
static constexpr uint8_t states[] = {
|
||||
Line::IOREQ | Line::RD,
|
||||
Line::CLK | Line::IOREQ | Line::RD,
|
||||
0,
|
||||
};
|
||||
return states;
|
||||
}
|
||||
|
||||
//
|
||||
// Output cycle.
|
||||
//
|
||||
|
||||
case Operation::OutputStart: {
|
||||
static constexpr uint8_t states[] = {
|
||||
Line::CLK,
|
||||
0,
|
||||
Line::CLK | Line::IOREQ | Line::WR,
|
||||
};
|
||||
return states;
|
||||
}
|
||||
|
||||
case Operation::OutputWait: {
|
||||
static constexpr uint8_t states[] = {
|
||||
Line::IOREQ | Line::WR,
|
||||
Line::CLK | Line::IOREQ | Line::WR,
|
||||
};
|
||||
return states;
|
||||
}
|
||||
|
||||
case Operation::Output: {
|
||||
static constexpr uint8_t states[] = {
|
||||
Line::IOREQ | Line::WR,
|
||||
Line::CLK | Line::IOREQ | Line::WR,
|
||||
0,
|
||||
};
|
||||
return states;
|
||||
}
|
||||
|
||||
//
|
||||
// TODO: Interrupt acknowledge.
|
||||
//
|
||||
|
||||
//
|
||||
// Bus acknowldge.
|
||||
//
|
||||
|
||||
case Operation::BusAcknowledge: {
|
||||
static constexpr uint8_t states[] = {
|
||||
Line::CLK | Line::BUSACK,
|
||||
Line::BUSACK,
|
||||
};
|
||||
return states;
|
||||
}
|
||||
|
||||
//
|
||||
// Internal.
|
||||
//
|
||||
|
||||
case Operation::Internal: {
|
||||
static constexpr uint8_t states[] = {
|
||||
Line::CLK, 0,
|
||||
Line::CLK, 0,
|
||||
Line::CLK, 0,
|
||||
Line::CLK, 0,
|
||||
Line::CLK, 0,
|
||||
};
|
||||
return states;
|
||||
}
|
||||
|
||||
default: break;
|
||||
}
|
||||
|
||||
return nullptr;
|
||||
}
|
||||
|
||||
PartialMachineCycle(const PartialMachineCycle &rhs) noexcept;
|
||||
PartialMachineCycle(Operation operation, HalfCycles length, uint16_t *address, uint8_t *value, bool was_requested) noexcept;
|
||||
PartialMachineCycle() noexcept;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user