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Implements the first few addressing modes for TST.

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This commit is contained in:
Thomas Harte 2019-04-15 10:03:52 -04:00
parent 3d240f3f18
commit 328d297490
3 changed files with 64 additions and 0 deletions
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22
Processors/68000/Implementation/68000Implementation.hpp
View File

@ -767,6 +767,28 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
#undef set_flags_w #undef set_flags_w
#undef set_flags_l #undef set_flags_l
/*
TSTs: compare to zero.
*/
case Operation::TSTb:
carry_flag_ = overflow_flag_ = 0;
zero_result_ = active_program_->source->halves.low.halves.low;
negative_flag_ = zero_result_ & 0x80;
break;
case Operation::TSTw:
carry_flag_ = overflow_flag_ = 0;
zero_result_ = active_program_->source->halves.low.full;
negative_flag_ = zero_result_ & 0x8000;
break;
case Operation::TSTl:
carry_flag_ = overflow_flag_ = 0;
zero_result_ = active_program_->source->full;
negative_flag_ = zero_result_ & 0x80000000;
break;
/* /*
Development period debugging. Development period debugging.
*/ */

40
Processors/68000/Implementation/68000Storage.cpp
View File

@ -326,6 +326,8 @@ struct ProcessorStorageConstructor {
MOVEM, // Maps a mode and register as they were a 'destination' and sets up bus steps with a suitable MOVEM, // Maps a mode and register as they were a 'destination' and sets up bus steps with a suitable
// hole for the runtime part to install proper MOVEM activity. // hole for the runtime part to install proper MOVEM activity.
TST, // Mapsa mode and register to a TST.
}; };
using Operation = ProcessorStorage::Operation; using Operation = ProcessorStorage::Operation;
@ -467,6 +469,10 @@ struct ProcessorStorageConstructor {
{0xffc0, 0x4880, Operation::MOVEMtoMw, Decoder::MOVEM}, // 4-128 (p232) {0xffc0, 0x4880, Operation::MOVEMtoMw, Decoder::MOVEM}, // 4-128 (p232)
{0xffc0, 0x4cc0, Operation::MOVEMtoRl, Decoder::MOVEM}, // 4-128 (p232) {0xffc0, 0x4cc0, Operation::MOVEMtoRl, Decoder::MOVEM}, // 4-128 (p232)
{0xffc0, 0x4c80, Operation::MOVEMtoRw, Decoder::MOVEM}, // 4-128 (p232) {0xffc0, 0x4c80, Operation::MOVEMtoRw, Decoder::MOVEM}, // 4-128 (p232)
{0xffc0, 0x4a00, Operation::TSTb, Decoder::TST}, // 4-192 (p296)
{0xffc0, 0x4a40, Operation::TSTw, Decoder::TST}, // 4-192 (p296)
{0xffc0, 0x4a80, Operation::TSTl, Decoder::TST}, // 4-192 (p296)
}; };
#ifndef NDEBUG #ifndef NDEBUG
@ -2168,6 +2174,40 @@ struct ProcessorStorageConstructor {
op(Action::None, seq("nn _ np")); op(Action::None, seq("nn _ np"));
break; break;
case Decoder::TST: {
storage_.instructions[instruction].set_source(storage_, ea_mode, ea_register);
const int mode = combined_mode(ea_mode, ea_register);
const bool is_byte_access = operation == Operation::TSTb;
const bool is_long_word_access = operation == Operation::TSTl;
switch(is_long_word_access ? l(mode) : bw(mode)) {
default: continue;
case bw(Dn):
case l(Dn):
op(Action::PerformOperation, seq("np"));
break;
case bw(Ind):
case bw(PostInc):
op(Action::None, seq("nr", { a(ea_register) }, !is_byte_access));
op(Action::PerformOperation, seq("np"));
if(mode == PostInc) {
op(int(is_byte_access ? Action::Increment1 : Action::Increment2) | MicroOp::SourceMask);
}
break;
case l(Ind):
case l(PostInc):
op(int(Action::CopyToEffectiveAddress) | MicroOp::SourceMask, seq("nR+ nr", { ea(0), ea(0) }));
op(Action::PerformOperation, seq("np"));
if(mode == PostInc) {
op(int(Action::Increment4) | MicroOp::SourceMask);
}
break;
}
} break;
default: default:
std::cerr << "Unhandled decoder " << int(mapping.decoder) << std::endl; std::cerr << "Unhandled decoder " << int(mapping.decoder) << std::endl;
continue; continue;

2
Processors/68000/Implementation/68000Storage.hpp
View File

@ -82,6 +82,8 @@ class ProcessorStorage {
MOVEMtoMl, MOVEMtoMw, MOVEMtoMl, MOVEMtoMw,
Scc, Scc,
TSTb, TSTw, TSTl,
}; };
/*! /*!