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Further correct R15 as a destination.

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This commit is contained in:
Thomas Harte 2024-03-10 22:56:02 -04:00
parent bd62228cc6
commit 336292bc49
2 changed files with 10 additions and 8 deletions
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11
InstructionSets/ARM/Executor.hpp
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@ -175,6 +175,7 @@ struct Executor {
break; break;
} }
const bool writes_pc = !is_comparison(flags.operation()) && fields.destination() == 15;
if constexpr (flags.set_condition_codes()) { if constexpr (flags.set_condition_codes()) {
// "When Rd is a register other than R15, the condition code flags in the PSR may be // "When Rd is a register other than R15, the condition code flags in the PSR may be
// updated from the ALU flags as described above. When Rd is R15 and the S flag in // updated from the ALU flags as described above. When Rd is R15 and the S flag in
@ -185,11 +186,9 @@ struct Executor {
// this case to update those PSR flags which are not protected by virtue of the // this case to update those PSR flags which are not protected by virtue of the
// processor mode." // processor mode."
if(fields.destination() == 15) { if(writes_pc) {
registers_.set_status(conditions); registers_.set_status(pc_proxy);
if constexpr (!is_comparison(flags.operation())) { registers_.set_pc(pc_proxy);
registers_.set_pc(pc_proxy);
}
} else { } else {
// Set N and Z in a unified way. // Set N and Z in a unified way.
registers_.set_nz(conditions); registers_.set_nz(conditions);
@ -201,7 +200,7 @@ struct Executor {
} }
} else { } else {
// "If the S flag is clear when Rd is R15, only the 24 PC bits of R15 will be written." // "If the S flag is clear when Rd is R15, only the 24 PC bits of R15 will be written."
if(fields.destination() == 15 && !is_comparison(flags.operation())) { if(writes_pc) {
registers_.set_pc(pc_proxy); registers_.set_pc(pc_proxy);
} }
} }

7
OSBindings/Mac/Clock SignalTests/ARMDecoderTests.mm
View File

@ -396,7 +396,7 @@ struct MemoryLedger {
// sheet specifically says for a shift-by-register that // sheet specifically says for a shift-by-register that
// "LSL by more than 32 has result zero, carry out zero" so I think // "LSL by more than 32 has result zero, carry out zero" so I think
// the test set is adrift on the following: // the test set is adrift on the following:
ignore_test = test_count == 15 - 1; ignore_test = regs[2] >= 32;
break; break;
case 0xe090e00f: case 0xe090e00f:
@ -414,6 +414,9 @@ struct MemoryLedger {
auto &registers = test->registers(); auto &registers = test->registers();
if(label == "Before:") { if(label == "Before:") {
// This is the start of a new test. // This is the start of a new test.
// TODO: establish implicit register values?
// Apply provided state.
registers.set_mode(Mode::Supervisor); // To make sure the actual mode is applied. registers.set_mode(Mode::Supervisor); // To make sure the actual mode is applied.
registers.set_pc(regs[15] - 8); registers.set_pc(regs[15] - 8);
registers.set_status(regs[15]); registers.set_status(regs[15]);
@ -427,7 +430,7 @@ struct MemoryLedger {
continue; continue;
} }
if(instruction == 0xe4931000 && test_count == 3) { if(instruction == 0xe33ef000 && test_count == 1) {
printf(""); printf("");
} }