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Further correct R15 as a destination.
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@ -175,6 +175,7 @@ struct Executor {
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break;
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}
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const bool writes_pc = !is_comparison(flags.operation()) && fields.destination() == 15;
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if constexpr (flags.set_condition_codes()) {
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// "When Rd is a register other than R15, the condition code flags in the PSR may be
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// updated from the ALU flags as described above. When Rd is R15 and the S flag in
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@ -185,11 +186,9 @@ struct Executor {
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// this case to update those PSR flags which are not protected by virtue of the
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// processor mode."
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if(fields.destination() == 15) {
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registers_.set_status(conditions);
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if constexpr (!is_comparison(flags.operation())) {
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if(writes_pc) {
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registers_.set_status(pc_proxy);
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registers_.set_pc(pc_proxy);
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}
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} else {
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// Set N and Z in a unified way.
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registers_.set_nz(conditions);
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@ -201,7 +200,7 @@ struct Executor {
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}
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} else {
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// "If the S flag is clear when Rd is R15, only the 24 PC bits of R15 will be written."
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if(fields.destination() == 15 && !is_comparison(flags.operation())) {
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if(writes_pc) {
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registers_.set_pc(pc_proxy);
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}
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}
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@ -396,7 +396,7 @@ struct MemoryLedger {
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// sheet specifically says for a shift-by-register that
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// "LSL by more than 32 has result zero, carry out zero" so I think
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// the test set is adrift on the following:
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ignore_test = test_count == 15 - 1;
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ignore_test = regs[2] >= 32;
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break;
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case 0xe090e00f:
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@ -414,6 +414,9 @@ struct MemoryLedger {
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auto ®isters = test->registers();
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if(label == "Before:") {
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// This is the start of a new test.
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// TODO: establish implicit register values?
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// Apply provided state.
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registers.set_mode(Mode::Supervisor); // To make sure the actual mode is applied.
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registers.set_pc(regs[15] - 8);
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registers.set_status(regs[15]);
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@ -427,7 +430,7 @@ struct MemoryLedger {
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continue;
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}
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if(instruction == 0xe4931000 && test_count == 3) {
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if(instruction == 0xe33ef000 && test_count == 1) {
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printf("");
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}
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