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mirror of https://github.com/TomHarte/CLK.git synced 2024-11-28 21:49:27 +00:00

The Yamaha chips have more ports.

This commit is contained in:
Thomas Harte 2023-01-17 22:29:17 -05:00
parent f0b1c34db2
commit 339086d597

View File

@ -568,6 +568,11 @@ class ConcreteMachine:
case CPU::Z80::PartialMachineCycle::Input:
switch(address & 0xff) {
case 0x9a: case 0x9b:
if constexpr (vdp_model() == TI::TMS::TMS9918A) {
break;
}
[[fallthrough]];
case 0x98: case 0x99:
*cycle.value = vdp_->read(address);
z80_.set_interrupt_line(vdp_->get_interrupt_line());
@ -600,6 +605,11 @@ class ConcreteMachine:
case CPU::Z80::PartialMachineCycle::Output: {
const int port = address & 0xff;
switch(port) {
case 0x9a: case 0x9b:
if constexpr (vdp_model() == TI::TMS::TMS9918A) {
break;
}
[[fallthrough]];
case 0x98: case 0x99:
vdp_->write(address, *cycle.value);
z80_.set_interrupt_line(vdp_->get_interrupt_line());