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mirror of https://github.com/TomHarte/CLK.git synced 2024-11-28 21:49:27 +00:00

Don't post contended accesses other than on the +2a/+3.

Those machines have an actual latch for this stuff, the others don't.
This commit is contained in:
Thomas Harte 2021-04-15 21:13:06 -04:00
parent b2cf121410
commit 349b9ce502

View File

@ -323,9 +323,11 @@ template<Model model> class ConcreteMachine:
case PartialMachineCycle::Read: case PartialMachineCycle::Read:
*cycle.value = read_pointers_[address >> 14][address]; *cycle.value = read_pointers_[address >> 14][address];
if constexpr (model >= Model::Plus2a) {
if(is_contended_[address >> 14]) { if(is_contended_[address >> 14]) {
video_->set_last_contended_area_access(*cycle.value); video_->set_last_contended_area_access(*cycle.value);
} }
}
break; break;
case PartialMachineCycle::Write: case PartialMachineCycle::Write:
@ -336,10 +338,12 @@ template<Model model> class ConcreteMachine:
write_pointers_[address >> 14][address] = *cycle.value; write_pointers_[address >> 14][address] = *cycle.value;
if constexpr (model >= Model::Plus2a) {
// Fill the floating bus buffer if this write is within the contended area. // Fill the floating bus buffer if this write is within the contended area.
if(is_contended_[address >> 14]) { if(is_contended_[address >> 14]) {
video_->set_last_contended_area_access(*cycle.value); video_->set_last_contended_area_access(*cycle.value);
} }
}
break; break;
case PartialMachineCycle::Output: case PartialMachineCycle::Output: