6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2025-08-13 00:25:26 +00:00
Code Issues Projects Releases Wiki Activity

Ensures a trailing zero bit isn't dropped.

Browse Source
This commit is contained in:
Thomas Harte
2019-07-16 16:36:00 -04:00
parent cb16790330
commit 3633285aaa
1 changed files with 2 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
Storage/Disk/Track/TrackSerialiser.cpp
View File

@@ -40,12 +40,13 @@ Storage::Disk::PCMSegment Storage::Disk::track_serialisation(const Track &track,
Time time_error = Time(0); Time time_error = Time(0);
while(true) { while(true) {
Track::Event next_event = track_copy->get_next_event(); Track::Event next_event = track_copy->get_next_event();
if(next_event.type == Track::Event::IndexHole) break;
Time extended_length = next_event.length * length_multiplier + time_error; Time extended_length = next_event.length * length_multiplier + time_error;
time_error.clock_rate = extended_length.clock_rate; time_error.clock_rate = extended_length.clock_rate;
time_error.length = extended_length.length % extended_length.clock_rate; time_error.length = extended_length.length % extended_length.clock_rate;
pll.run_for(Cycles(static_cast<int>(extended_length.get<int64_t>()))); pll.run_for(Cycles(static_cast<int>(extended_length.get<int64_t>())));
if(next_event.type == Track::Event::IndexHole) break;
pll.add_pulse(); pll.add_pulse();
// If the PLL is now sufficiently primed, restart, and start recording bits this time. // If the PLL is now sufficiently primed, restart, and start recording bits this time.