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mirror of https://github.com/TomHarte/CLK.git synced 2026-04-20 10:17:05 +00:00

Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests.

This commit is contained in:
Thomas Harte
2017-07-27 20:17:13 -04:00
parent 25fd95044c
commit 37950143fc
10 changed files with 49 additions and 39 deletions
+1 -1
View File
@@ -25,7 +25,7 @@ void AllRAMProcessor::get_data_at_address(uint16_t startAddress, size_t length,
memcpy(data, &memory_[startAddress], endAddress - startAddress);
}
uint32_t AllRAMProcessor::get_timestamp() {
HalfCycles AllRAMProcessor::get_timestamp() {
return timestamp_;
}