6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-23 03:32:32 +00:00
Code Issues Projects Releases Wiki Activity

Test and correct Bcc, BSR, CLR, NEGX, NEG.

Browse Source
This commit is contained in:
Thomas Harte 2022-04-20 20:19:56 -04:00
parent fa4dee8cfd
commit 3af93ada6f
2 changed files with 23 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
InstructionSets/68k/Decoder.cpp
View File

@ -316,6 +316,9 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::validated
}
case OpT(Operation::Scc):
case OpT(Operation::NEGXb): case OpT(Operation::NEGXw): case OpT(Operation::NEGXl):
case OpT(Operation::CLRb): case OpT(Operation::CLRw): case OpT(Operation::CLRl):
case OpT(Operation::NEGb): case OpT(Operation::NEGw): case OpT(Operation::NEGl):
switch(original.mode<0>()) {
default: return original;

27
OSBindings/Mac/Clock SignalTests/m68kDecoderTests.mm
View File

@ -155,16 +155,29 @@ template <int index> NSString *operand(Preinstruction instruction) {
case Operation::DBcc: instruction = @"DBcc"; break;
case Operation::Scc: instruction = @"Scc"; break;
case Operation::Bccb:
case Operation::Bccl:
case Operation::Bccw: instruction = @"Bcc"; break;
case Operation::BSRb:
case Operation::BSRl:
case Operation::BSRw: instruction = @"BSR"; break;
case Operation::CLRb: instruction = @"CLR.b"; break;
case Operation::CLRw: instruction = @"CLR.w"; break;
case Operation::CLRl: instruction = @"CLR.l"; break;
case Operation::NEGXb: instruction = @"NEGX.b"; break;
case Operation::NEGXw: instruction = @"NEGX.w"; break;
case Operation::NEGXl: instruction = @"NEGX.l"; break;
case Operation::NEGb: instruction = @"NEG.b"; break;
case Operation::NEGw: instruction = @"NEG.w"; break;
case Operation::NEGl: instruction = @"NEG.l"; break;
/*
TODO:
Bccb, Bccl, Bccw,
BSRb, BSRl, BSRw,
CLRb, CLRw, CLRl,
NEGXb, NEGXw, NEGXl,
NEGb, NEGw, NEGl,
ASLb, ASLw, ASLl, ASLm,
ASRb, ASRw, ASRl, ASRm,
LSLb, LSLw, LSLl, LSLm,