diff --git a/Processors/6502Esque/6502Esque.hpp b/Processors/6502Esque/6502Esque.hpp index e9fd9d9ee..900ac8c6a 100644 --- a/Processors/6502Esque/6502Esque.hpp +++ b/Processors/6502Esque/6502Esque.hpp @@ -79,37 +79,39 @@ enum BusOperation { /// 6502: never signalled. /// 65816: indicates that a read was signalled with VPB. ReadVector, + /// 6502: never signalled. + /// 65816: indicates that a read was signalled, but neither VDA nor VPA were active. + InternalOperationRead, /// 6502: indicates that a write was signalled. /// 65816: indicates that a write was signalled with VDA. Write, + /// 6502: never signalled. + /// 65816: indicates that a write was signalled, but neither VDA nor VPA were active. + InternalOperationWrite, - /// All processors: indicates that the processor is holding state due to the RDY input. + /// All processors: indicates that the processor is paused due to the RDY input. /// 65C02 and 65816: indicates a WAI is ongoing. Ready, - /// 6502: never signalled. - /// 65816: indicates that a read was signalled, but neither VDA or VPA were active. - InternalOperation, - /// 65C02 and 65816: indicates a STP condition. None, }; /*! - Evaluates to @c true if the operation is any sort of read; @c false otherwise. + For a machine watching only the RWB line, evaluates to @c true if the operation should be treated as a read; @c false otherwise. */ -#define isReadOperation(v) (v < CPU::MOS6502Esque::BusOperation::Write) +#define isReadOperation(v) (v < CPU::MOS6502Esque::Write) /*! - Evaluates to @c true if the operation is any sort of write; @c false otherwise. + For a machine watching only the RWB line, evaluates to @c true if the operation is any sort of write; @c false otherwise. */ -#define isWriteOperation(v) (v == CPU::MOS6502Esque::BusOperation::Write) +#define isWriteOperation(v) (v == CPU::MOS6502Esque::Write || v == CPU::MOS6502Esque::InternalOperationWrite) /*! - Evaluates to @c true if the operation is any sort of memory access; @c false otherwise. + Evaluates to @c true if the operation actually expects a response; @c false otherwise. */ -#define isAccessOperation(v) (v < CPU::MOS6502Esque::BusOperation::Ready) +#define isAccessOperation(v) ((v < CPU::MOS6502Esque::Ready) && (v != CPU::MOS6502Esque::InternalOperationRead) && (v != CPU::MOS6502Esque::InternalOperationWrite)) /*! A class providing empty implementations of the methods a 6502 uses to access the bus. To wire the 6502 to a bus, diff --git a/Processors/65816/Implementation/65816Implementation.hpp b/Processors/65816/Implementation/65816Implementation.hpp index c536ea818..157563a20 100644 --- a/Processors/65816/Implementation/65816Implementation.hpp +++ b/Processors/65816/Implementation/65816Implementation.hpp @@ -70,22 +70,22 @@ template void Processor void Processor void Processor void Processor void Processor &target) { - target(OperationSetMemoryLock); + target(OperationSetMemoryLock); // Set the memory lock output until the end of this instruction. if(!is8bit) target(CycleFetchIncrementData); // Data low. target(CycleFetchData); // Data [high]. - // TODO: does this look like another read? Or if VDA and VPA are both low, does the 65816 actually do no access? if(!is8bit) target(CycleFetchDataThrowaway); // 16-bit: reread final byte of data. else target(CycleStoreDataThrowaway); // 8-bit rewrite final byte of data. @@ -182,7 +181,7 @@ struct CPU::WDC65816::ProcessorStorageConstructor { // 1b. Absolute; a, JMP. static void absolute_jmp(AccessType, bool, const std::function &target) { - target(CycleFetchIncrementPC); // New PCL. + target(CycleFetchIncrementPC); // New PCL.] target(CycleFetchPC); // New PCH. target(OperationPerform); // [JMP] } @@ -199,9 +198,9 @@ struct CPU::WDC65816::ProcessorStorageConstructor { // 1d. Absolute; a, read-modify-write. static void absolute_rmw(AccessType, bool is8bit, const std::function &target) { - target(CycleFetchIncrementPC); // AAL. - target(CycleFetchIncrementPC); // AAH. - target(OperationConstructAbsolute); // Calculate data address. + target(CycleFetchIncrementPC); // AAL. + target(CycleFetchIncrementPC); // AAH. + target(OperationConstructAbsolute); // Calculate data address. read_modify_write(is8bit, target); } @@ -382,10 +381,10 @@ struct CPU::WDC65816::ProcessorStorageConstructor { // 10a. Direct; d. // (That's zero page in 6502 terms) static void direct(AccessType type, bool is8bit, const std::function &target) { - target(CycleFetchIncrementPC); // DO. + target(CycleFetchIncrementPC); // DO. target(OperationConstructDirect); - target(CycleFetchPCThrowaway); // IO. + target(CycleFetchPCThrowaway); // IO. read_write(type, is8bit, target); } @@ -594,9 +593,8 @@ struct CPU::WDC65816::ProcessorStorageConstructor { target(CyclePush); // PCL target(CyclePush); // P - // TODO: I think I need a seperate vector fetch here, to signal vector pull? - target(CycleFetchIncrementData); // AAVL - target(CycleFetchData); // AAVH + target(CycleFetchIncrementVector); // AAVL + target(CycleFetchVector); // AAVH target(OperationPerform); // Jumps to the vector address. } @@ -704,9 +702,8 @@ struct CPU::WDC65816::ProcessorStorageConstructor { target(CyclePush); // PCL target(CyclePush); // P - // TODO: I think I need a seperate vector fetch here, to signal vector pull? - target(CycleFetchIncrementData); // AAVL - target(CycleFetchData); // AAVH + target(CycleFetchIncrementVector); // AAVL + target(CycleFetchVector); // AAVH target(OperationPerform); // Jumps to the vector address. } diff --git a/Processors/65816/Implementation/65816Storage.hpp b/Processors/65816/Implementation/65816Storage.hpp index 4bc731372..4edf9cf76 100644 --- a/Processors/65816/Implementation/65816Storage.hpp +++ b/Processors/65816/Implementation/65816Storage.hpp @@ -25,6 +25,10 @@ enum MicroOp: uint8_t { CycleFetchIncorrectDataAddress, /// Fetches a byte from the data address and throws it away. CycleFetchDataThrowaway, + /// Fetches a byte from the data address to the data buffer, signalling VPB . + CycleFetchVector, + /// Fetches a byte from the data address to the data buffer and increments the data address, signalling VPB. + CycleFetchIncrementVector, // Dedicated block-move cycles; these use the data buffer as an intermediary. CycleFetchBlockX,