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Attempts to complete all 65816 bus signalling.
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Thomas Harte
parent
096add7551
commit
3b398f7a9a
@ -79,37 +79,39 @@ enum BusOperation {
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/// 6502: never signalled.
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/// 65816: indicates that a read was signalled with VPB.
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ReadVector,
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/// 6502: never signalled.
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/// 65816: indicates that a read was signalled, but neither VDA nor VPA were active.
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InternalOperationRead,
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/// 6502: indicates that a write was signalled.
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/// 65816: indicates that a write was signalled with VDA.
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Write,
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/// 6502: never signalled.
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/// 65816: indicates that a write was signalled, but neither VDA nor VPA were active.
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InternalOperationWrite,
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/// All processors: indicates that the processor is holding state due to the RDY input.
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/// All processors: indicates that the processor is paused due to the RDY input.
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/// 65C02 and 65816: indicates a WAI is ongoing.
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Ready,
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/// 6502: never signalled.
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/// 65816: indicates that a read was signalled, but neither VDA or VPA were active.
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InternalOperation,
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/// 65C02 and 65816: indicates a STP condition.
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None,
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};
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/*!
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Evaluates to @c true if the operation is any sort of read; @c false otherwise.
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For a machine watching only the RWB line, evaluates to @c true if the operation should be treated as a read; @c false otherwise.
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*/
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#define isReadOperation(v) (v < CPU::MOS6502Esque::BusOperation::Write)
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#define isReadOperation(v) (v < CPU::MOS6502Esque::Write)
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/*!
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Evaluates to @c true if the operation is any sort of write; @c false otherwise.
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For a machine watching only the RWB line, evaluates to @c true if the operation is any sort of write; @c false otherwise.
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*/
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#define isWriteOperation(v) (v == CPU::MOS6502Esque::BusOperation::Write)
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#define isWriteOperation(v) (v == CPU::MOS6502Esque::Write || v == CPU::MOS6502Esque::InternalOperationWrite)
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/*!
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Evaluates to @c true if the operation is any sort of memory access; @c false otherwise.
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Evaluates to @c true if the operation actually expects a response; @c false otherwise.
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*/
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#define isAccessOperation(v) (v < CPU::MOS6502Esque::BusOperation::Ready)
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#define isAccessOperation(v) ((v < CPU::MOS6502Esque::Ready) && (v != CPU::MOS6502Esque::InternalOperationRead) && (v != CPU::MOS6502Esque::InternalOperationWrite))
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/*!
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A class providing empty implementations of the methods a 6502 uses to access the bus. To wire the 6502 to a bus,
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@ -70,22 +70,22 @@ template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler,
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// PC fetches.
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//
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case CycleFetchIncrementPC:
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read(registers_.pc | registers_.program_bank, instruction_buffer_.next_input());
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++registers_.pc;
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break;
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case CycleFetchOpcode:
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perform_bus(registers_.pc | registers_.program_bank, instruction_buffer_.next_input(), MOS6502Esque::ReadOpcode);
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++registers_.pc;
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break;
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case CycleFetchIncrementPC:
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perform_bus(registers_.pc | registers_.program_bank, instruction_buffer_.next_input(), MOS6502Esque::ReadProgram);
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++registers_.pc;
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break;
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case CycleFetchPC:
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read(registers_.pc | registers_.program_bank, instruction_buffer_.next_input());
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perform_bus(registers_.pc | registers_.program_bank, instruction_buffer_.next_input(), MOS6502Esque::ReadProgram);
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break;
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case CycleFetchPCThrowaway:
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read(registers_.pc | registers_.program_bank, &bus_throwaway_);
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perform_bus(registers_.pc | registers_.program_bank, &bus_throwaway_, MOS6502Esque::InternalOperationRead);
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break;
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//
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@ -101,11 +101,11 @@ template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler,
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break;
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case CycleFetchDataThrowaway:
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read(data_address_, &bus_throwaway_);
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perform_bus(data_address_, &bus_throwaway_, MOS6502Esque::InternalOperationRead);
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break;
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case CycleFetchIncorrectDataAddress:
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read(incorrect_data_address_, &bus_throwaway_);
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perform_bus(incorrect_data_address_, &bus_throwaway_, MOS6502Esque::InternalOperationRead);
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break;
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case CycleFetchIncrementData:
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@ -113,12 +113,21 @@ template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler,
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increment_data_address();
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break;
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case CycleFetchVector:
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perform_bus(data_address_, data_buffer_.next_input(), MOS6502Esque::ReadVector);
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break;
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case CycleFetchIncrementVector:
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perform_bus(data_address_, data_buffer_.next_input(), MOS6502Esque::ReadVector);
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increment_data_address();
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break;
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case CycleStoreData:
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write(data_address_, data_buffer_.next_output());
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break;
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case CycleStoreDataThrowaway:
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write(data_address_, data_buffer_.preview_output());
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perform_bus(data_address_, data_buffer_.preview_output(), MOS6502Esque::InternalOperationWrite);
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break;
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case CycleStoreIncrementData:
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@ -136,7 +145,7 @@ template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler,
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break;
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case CycleFetchBlockY:
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read(((instruction_buffer_.value & 0xff00) << 8) | y(), &bus_throwaway_);
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perform_bus(((instruction_buffer_.value & 0xff00) << 8) | y(), &bus_throwaway_, MOS6502Esque::InternalOperationRead);
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break;
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case CycleStoreBlockY:
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@ -172,7 +181,7 @@ template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler,
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break;
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case CycleAccessStack:
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stack_access(&bus_throwaway_, MOS6502Esque::Read);
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stack_access(&bus_throwaway_, MOS6502Esque::InternalOperationRead);
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break;
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#undef stack_access
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@ -156,12 +156,11 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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}
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static void read_modify_write(bool is8bit, const std::function<void(MicroOp)> &target) {
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target(OperationSetMemoryLock);
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target(OperationSetMemoryLock); // Set the memory lock output until the end of this instruction.
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if(!is8bit) target(CycleFetchIncrementData); // Data low.
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target(CycleFetchData); // Data [high].
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// TODO: does this look like another read? Or if VDA and VPA are both low, does the 65816 actually do no access?
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if(!is8bit) target(CycleFetchDataThrowaway); // 16-bit: reread final byte of data.
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else target(CycleStoreDataThrowaway); // 8-bit rewrite final byte of data.
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@ -182,7 +181,7 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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// 1b. Absolute; a, JMP.
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static void absolute_jmp(AccessType, bool, const std::function<void(MicroOp)> &target) {
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target(CycleFetchIncrementPC); // New PCL.
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target(CycleFetchIncrementPC); // New PCL.]
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target(CycleFetchPC); // New PCH.
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target(OperationPerform); // [JMP]
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}
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@ -199,9 +198,9 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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// 1d. Absolute; a, read-modify-write.
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static void absolute_rmw(AccessType, bool is8bit, const std::function<void(MicroOp)> &target) {
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target(CycleFetchIncrementPC); // AAL.
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target(CycleFetchIncrementPC); // AAH.
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target(OperationConstructAbsolute); // Calculate data address.
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target(CycleFetchIncrementPC); // AAL.
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target(CycleFetchIncrementPC); // AAH.
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target(OperationConstructAbsolute); // Calculate data address.
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read_modify_write(is8bit, target);
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}
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@ -382,10 +381,10 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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// 10a. Direct; d.
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// (That's zero page in 6502 terms)
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static void direct(AccessType type, bool is8bit, const std::function<void(MicroOp)> &target) {
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target(CycleFetchIncrementPC); // DO.
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target(CycleFetchIncrementPC); // DO.
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target(OperationConstructDirect);
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target(CycleFetchPCThrowaway); // IO.
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target(CycleFetchPCThrowaway); // IO.
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read_write(type, is8bit, target);
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}
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@ -594,9 +593,8 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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target(CyclePush); // PCL
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target(CyclePush); // P
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// TODO: I think I need a seperate vector fetch here, to signal vector pull?
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target(CycleFetchIncrementData); // AAVL
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target(CycleFetchData); // AAVH
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target(CycleFetchIncrementVector); // AAVL
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target(CycleFetchVector); // AAVH
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target(OperationPerform); // Jumps to the vector address.
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}
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@ -704,9 +702,8 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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target(CyclePush); // PCL
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target(CyclePush); // P
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// TODO: I think I need a seperate vector fetch here, to signal vector pull?
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target(CycleFetchIncrementData); // AAVL
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target(CycleFetchData); // AAVH
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target(CycleFetchIncrementVector); // AAVL
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target(CycleFetchVector); // AAVH
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target(OperationPerform); // Jumps to the vector address.
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}
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@ -25,6 +25,10 @@ enum MicroOp: uint8_t {
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CycleFetchIncorrectDataAddress,
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/// Fetches a byte from the data address and throws it away.
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CycleFetchDataThrowaway,
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/// Fetches a byte from the data address to the data buffer, signalling VPB .
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CycleFetchVector,
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/// Fetches a byte from the data address to the data buffer and increments the data address, signalling VPB.
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CycleFetchIncrementVector,
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// Dedicated block-move cycles; these use the data buffer as an intermediary.
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CycleFetchBlockX,
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