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Add MULU/S functionality, though not timing.
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@ -162,6 +162,7 @@ enum ExecutionState: int {
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MOVEMtoM_finish,
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DIVU_DIVS,
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MULU_MULS,
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};
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// MARK: - The state machine.
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@ -697,6 +698,8 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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StdCASE(DIVU, perform_state_ = DIVU_DIVS);
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StdCASE(DIVS, perform_state_ = DIVU_DIVS);
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StdCASE(MULU, perform_state_ = MULU_MULS);
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StdCASE(MULS, perform_state_ = MULU_MULS);
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default:
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assert(false);
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@ -1854,6 +1857,24 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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Prefetch(); // np
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MoveToStateSpecific(Decode);
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//
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// MULU and MULS
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//
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BeginState(MULU_MULS):
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Prefetch(); // np
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// Perform the instruction.
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PerformDynamic();
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// Delay the correct amount of time.
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IdleBus(dynamic_instruction_length_);
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// MULU and MULS are always to a register, so just write back here
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// to save on dispatch costs.
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registers_[instruction_.reg(1)] = operand_[1];
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MoveToStateSpecific(Decode);
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//
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// Various states TODO.
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//
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@ -1951,6 +1972,14 @@ template <bool did_overflow> void ProcessorBase::did_divs(int32_t, int32_t) {
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// TODO: calculate cost.
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}
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template <typename IntT> void ProcessorBase::did_mulu(IntT) {
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// TODO: calculate cost.
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}
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template <typename IntT> void ProcessorBase::did_muls(IntT) {
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// TODO: calculate cost.
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}
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template <bool use_current_instruction_pc> void ProcessorBase::raise_exception(int vector) {
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// No overt action is taken here; instructions that might throw an exception are required
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// to check-in after the fact.
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@ -122,8 +122,8 @@ struct ProcessorBase: public InstructionSet::M68k::NullFlowController {
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// Flow controller... many TODO.
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using Preinstruction = InstructionSet::M68k::Preinstruction;
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template <typename IntT> void did_mulu(IntT) {} //
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template <typename IntT> void did_muls(IntT) {} //
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template <typename IntT> void did_mulu(IntT);
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template <typename IntT> void did_muls(IntT);
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inline void did_chk(bool, bool);
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inline void did_scc(bool);
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inline void did_shift(int) {} //
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