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Corrects the carry and extend flags for various long-word operations.

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This commit is contained in:
Thomas Harte 2019-04-21 22:08:18 -04:00
parent b78ea7d24c
commit 3cb042a49d
4 changed files with 19 additions and 26 deletions
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1
Machines/Electron/Electron.cpp
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@ -62,6 +62,7 @@ class ConcreteMachine:
set_clock_rate(2000000); set_clock_rate(2000000);
speaker_.set_input_rate(2000000 / SoundGenerator::clock_rate_divider); speaker_.set_input_rate(2000000 / SoundGenerator::clock_rate_divider);
speaker_.set_high_frequency_cutoff(7000);
std::vector<std::string> rom_names = {"basic.rom", "os.rom"}; std::vector<std::string> rom_names = {"basic.rom", "os.rom"};
if(target.has_adfs) { if(target.has_adfs) {

8
OSBindings/Mac/Clock SignalTests/EmuTOSTests.mm
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@ -72,20 +72,20 @@ class EmuTOS: public CPU::MC68000::BusHandler {
case Microcycle::SelectWord | Microcycle::Read: case Microcycle::SelectWord | Microcycle::Read:
cycle.value->full = is_peripheral ? peripheral_result : base[word_address]; cycle.value->full = is_peripheral ? peripheral_result : base[word_address];
if(!(cycle.operation & Microcycle::IsProgram)) printf("[word r %08x -> %04x] ", *cycle.address, cycle.value->full); // if(!(cycle.operation & Microcycle::IsProgram)) printf("[word r %08x -> %04x] ", *cycle.address, cycle.value->full);
break; break;
case Microcycle::SelectByte | Microcycle::Read: case Microcycle::SelectByte | Microcycle::Read:
cycle.value->halves.low = (is_peripheral ? peripheral_result : base[word_address]) >> cycle.byte_shift(); cycle.value->halves.low = (is_peripheral ? peripheral_result : base[word_address]) >> cycle.byte_shift();
if(!(cycle.operation & Microcycle::IsProgram)) printf("[byte r %08x -> %02x] ", *cycle.address, cycle.value->halves.low); // if(!(cycle.operation & Microcycle::IsProgram)) printf("[byte r %08x -> %02x] ", *cycle.address, cycle.value->halves.low);
break; break;
case Microcycle::SelectWord: case Microcycle::SelectWord:
assert(!(is_rom && !is_peripheral)); assert(!(is_rom && !is_peripheral));
if(!(cycle.operation & Microcycle::IsProgram)) printf("[word w %04x -> %08x] ", cycle.value->full, *cycle.address); // if(!(cycle.operation & Microcycle::IsProgram)) printf("[word w %04x -> %08x] ", cycle.value->full, *cycle.address);
base[word_address] = cycle.value->full; base[word_address] = cycle.value->full;
break; break;
case Microcycle::SelectByte: case Microcycle::SelectByte:
assert(!(is_rom && !is_peripheral)); assert(!(is_rom && !is_peripheral));
if(!(cycle.operation & Microcycle::IsProgram)) printf("[byte w %02x -> %08x] ", cycle.value->halves.low, *cycle.address); // if(!(cycle.operation & Microcycle::IsProgram)) printf("[byte w %02x -> %08x] ", cycle.value->halves.low, *cycle.address);
base[word_address] = (cycle.value->halves.low << cycle.byte_shift()) | (base[word_address] & (0xffff ^ cycle.byte_mask())); base[word_address] = (cycle.value->halves.low << cycle.byte_shift()) | (base[word_address] & (0xffff ^ cycle.byte_mask()));
break; break;
} }

8
OSBindings/Mac/Clock SignalTests/QLTests.mm
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@ -71,20 +71,20 @@ class QL: public CPU::MC68000::BusHandler {
case Microcycle::SelectWord | Microcycle::Read: case Microcycle::SelectWord | Microcycle::Read:
cycle.value->full = is_peripheral ? peripheral_result : base[word_address]; cycle.value->full = is_peripheral ? peripheral_result : base[word_address];
if(!(cycle.operation & Microcycle::IsProgram)) printf("\n[%08x -> %04x]\t", *cycle.address, cycle.value->full); if(!(cycle.operation & Microcycle::IsProgram)) printf("[%08x -> %04x] ", *cycle.address, cycle.value->full);
break; break;
case Microcycle::SelectByte | Microcycle::Read: case Microcycle::SelectByte | Microcycle::Read:
cycle.value->halves.low = (is_peripheral ? peripheral_result : base[word_address]) >> cycle.byte_shift(); cycle.value->halves.low = (is_peripheral ? peripheral_result : base[word_address]) >> cycle.byte_shift();
if(!(cycle.operation & Microcycle::IsProgram)) printf("\n[%08x -> %02x]\t", *cycle.address, cycle.value->halves.low); if(!(cycle.operation & Microcycle::IsProgram)) printf("[%08x -> %02x] ", *cycle.address, cycle.value->halves.low);
break; break;
case Microcycle::SelectWord: case Microcycle::SelectWord:
assert(!(is_rom && !is_peripheral)); assert(!(is_rom && !is_peripheral));
if(!(cycle.operation & Microcycle::IsProgram)) printf("\n{%04x -> %08x}\t", cycle.value->full, *cycle.address); if(!(cycle.operation & Microcycle::IsProgram)) printf("{%04x -> %08x} ", cycle.value->full, *cycle.address);
if(!is_peripheral) base[word_address] = cycle.value->full; if(!is_peripheral) base[word_address] = cycle.value->full;
break; break;
case Microcycle::SelectByte: case Microcycle::SelectByte:
assert(!(is_rom && !is_peripheral)); assert(!(is_rom && !is_peripheral));
if(!(cycle.operation & Microcycle::IsProgram)) printf("\n{%02x -> %08x}\t", cycle.value->halves.low, *cycle.address); if(!(cycle.operation & Microcycle::IsProgram)) printf("{%02x -> %08x} ", cycle.value->halves.low, *cycle.address);
if(!is_peripheral) base[word_address] = (cycle.value->halves.low << cycle.byte_shift()) | (base[word_address] & (0xffff ^ cycle.byte_mask())); if(!is_peripheral) base[word_address] = (cycle.value->halves.low << cycle.byte_shift()) | (base[word_address] & (0xffff ^ cycle.byte_mask()));
break; break;
} }

28
Processors/68000/Implementation/68000Implementation.hpp
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@ -52,30 +52,22 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
// no instruction was ongoing. Either way, do a standard instruction operation. // no instruction was ongoing. Either way, do a standard instruction operation.
// TODO: unless an interrupt is pending, or the trap flag is set. // TODO: unless an interrupt is pending, or the trap flag is set.
// if(program_counter_.full >= 0x250 && program_counter_.full <= 0x25e) {
// std::cout << std::setfill('0');
// std::cout << (extend_flag_ ? 'x' : '-') << (negative_flag_ ? 'n' : '-') << (zero_result_ ? '-' : 'z');
// std::cout << (overflow_flag_ ? 'v' : '-') << (carry_flag_ ? 'c' : '-') << '\t';
// for(int c = 0; c < 8; ++ c) std::cout << "d" << c << ":" << std::setw(8) << data_[c].full << " ";
// for(int c = 0; c < 8; ++ c) std::cout << "a" << c << ":" << std::setw(8) << address_[c].full << " ";
// }
static bool should_log = false; static bool should_log = false;
should_log |= program_counter_.full >= 0x4F54 && program_counter_.full <= 0x4F84; // should_log |= program_counter_.full >= 0x4F54 && program_counter_.full <= 0x4F84;
if(should_log) { // if(should_log) {
std::cout << "d0:" << std::setw(8) << std::setfill('0') << data_[0].full << " "; std::cout << std::setfill('0');
std::cout << "d1:" << std::setw(8) << std::setfill('0') << data_[1].full << " "; std::cout << (extend_flag_ ? 'x' : '-') << (negative_flag_ ? 'n' : '-') << (zero_result_ ? '-' : 'z');
std::cout << "d2:" << std::setw(8) << std::setfill('0') << data_[2].full << " "; std::cout << (overflow_flag_ ? 'v' : '-') << (carry_flag_ ? 'c' : '-') << '\t';
// std::cout << "a5:" << std::setw(8) << std::setfill('0') << address_[5].full << " "; for(int c = 0; c < 8; ++ c) std::cout << "d" << c << ":" << std::setw(8) << data_[c].full << " ";
// std::cout << "a6:" << std::setw(8) << std::setfill('0') << address_[6].full << " "; for(int c = 0; c < 8; ++ c) std::cout << "a" << c << ":" << std::setw(8) << address_[c].full << " ";
std::cout << "a7:" << std::setw(8) << std::setfill('0') << address_[7].full << " ";
if(is_supervisor_) { if(is_supervisor_) {
std::cout << "usp:" << std::setw(8) << std::setfill('0') << stack_pointers_[0].full << " "; std::cout << "usp:" << std::setw(8) << std::setfill('0') << stack_pointers_[0].full << " ";
} else { } else {
std::cout << "ssp:" << std::setw(8) << std::setfill('0') << stack_pointers_[1].full << " "; std::cout << "ssp:" << std::setw(8) << std::setfill('0') << stack_pointers_[1].full << " ";
} }
std::cout << '\n'; std::cout << '\n';
} // }
decoded_instruction_ = prefetch_queue_.halves.high.full; decoded_instruction_ = prefetch_queue_.halves.high.full;
if(!instructions[decoded_instruction_].micro_operations) { if(!instructions[decoded_instruction_].micro_operations) {
@ -157,7 +149,7 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
#define addsubl(a, b, dest, op, overflow) \ #define addsubl(a, b, dest, op, overflow) \
const auto source = a; \ const auto source = a; \
const auto destination = b; \ const auto destination = b; \
const uint64_t result = op(destination, source); \ const uint64_t result = op(uint64_t(destination), uint64_t(source)); \
\ \
zero_result_ = dest = uint32_t(result); \ zero_result_ = dest = uint32_t(result); \
extend_flag_ = carry_flag_ = result >> 32; \ extend_flag_ = carry_flag_ = result >> 32; \
@ -420,7 +412,7 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
case Operation::CMPl: { case Operation::CMPl: {
const uint32_t source = active_program_->source->full; const uint32_t source = active_program_->source->full;
const uint32_t destination = active_program_->destination->full; const uint32_t destination = active_program_->destination->full;
const uint64_t result = destination - source; const uint64_t result = uint64_t(destination) - uint64_t(source);
zero_result_ = uint32_t(result); zero_result_ = uint32_t(result);
carry_flag_ = result >> 32; carry_flag_ = result >> 32;