mirror of
https://github.com/TomHarte/CLK.git
synced 2025-04-06 10:38:16 +00:00
Relocate disk logic into a separate compilation unit.
This commit is contained in:
Thomas Harte
parent
1cf1c90511
commit
3ceb378b9b
@ -15,7 +15,6 @@
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#include <algorithm>
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#include <cassert>
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using namespace Amiga;
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namespace {
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@ -1093,59 +1092,6 @@ template <int sprite> void Chipset::TwoSpriteShifter::load(
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overflow_ |= uint8_t((new_data << 8) >> delay_shift);
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}
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// MARK: - Disk.
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void Chipset::DiskDMA::enqueue(uint16_t value, bool matches_sync) {
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if(matches_sync) {
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// TODO: start buffering from the next word onwards if
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// syncing is enabled.
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}
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// LOG("In: " << buffer_write_);
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buffer_[buffer_write_ & 3] = value;
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if(buffer_write_ == buffer_read_ + 4) {
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++buffer_read_;
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}
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++buffer_write_;
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}
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void Chipset::DiskDMA::set_length(uint16_t value) {
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if(value == last_set_length_) {
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dma_enable_ = value & 0x8000;
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write_ = value & 0x4000;
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length_ = value & 0x3fff;
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buffer_read_ = buffer_write_ = 0;
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if(dma_enable_) {
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LOG("Disk DMA " << (write_ ? "write" : "read") << " of " << length_ << " to " << PADHEX(8) << pointer_[0]);
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}
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}
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last_set_length_ = value;
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}
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bool Chipset::DiskDMA::advance() {
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if(!dma_enable_) return false;
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if(!write_) {
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if(length_ && buffer_read_ != buffer_write_) {
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ram_[pointer_[0] & ram_mask_] = buffer_[buffer_read_ & 3];
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++pointer_[0];
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++buffer_read_;
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--length_;
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if(!length_) {
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chipset_.posit_interrupt(InterruptFlag::DiskBlock);
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}
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return true;
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}
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}
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return false;
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}
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// MARK: - CRT connection.
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void Chipset::set_scan_target(Outputs::Display::ScanTarget *scan_target) {
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@ -1247,191 +1193,6 @@ void Chipset::set_component_prefers_clocking(ClockingHint::Source *, ClockingHin
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disk_controller_is_sleeping_ = preference == ClockingHint::Preference::None;
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}
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// MARK: - Disk Controller.
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Chipset::DiskController::DiskController(Cycles clock_rate, Chipset &chipset, DiskDMA &disk_dma, CIAB &cia) :
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Storage::Disk::Controller(clock_rate),
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chipset_(chipset),
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disk_dma_(disk_dma),
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cia_(cia) {
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// Add four drives.
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for(int c = 0; c < 4; c++) {
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emplace_drive(clock_rate.as<int>(), 300, 2, Storage::Disk::Drive::ReadyType::IBMRDY);
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}
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}
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void Chipset::DiskController::process_input_bit(int value) {
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data_ = uint16_t((data_ << 1) | value);
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++bit_count_;
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const bool sync_matches = data_ == sync_word_;
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if(sync_matches) {
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chipset_.posit_interrupt(InterruptFlag::DiskSyncMatch);
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if(sync_with_word_) {
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bit_count_ = 0;
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}
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}
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if(!(bit_count_ & 15)) {
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disk_dma_.enqueue(data_, sync_matches);
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}
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}
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void Chipset::DiskController::set_sync_word(uint16_t value) {
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LOG("Set disk sync word to " << PADHEX(4) << value);
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sync_word_ = value;
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}
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void Chipset::DiskController::set_control(uint16_t control) {
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// b13 and b14: precompensation length specifier
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// b12: 0 => GCR precompensation; 1 => MFM.
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// b10: 1 => enable use of word sync; 0 => disable.
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// b9: 1 => sync on MSB (Disk II style, presumably?); 0 => don't.
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// b8: 1 => 2µs per bit; 0 => 4µs.
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sync_with_word_ = control & 0x400;
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Storage::Time bit_length;
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bit_length.length = 1;
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bit_length.clock_rate = (control & 0x100) ? 500000 : 250000;
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set_expected_bit_length(bit_length);
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LOG((sync_with_word_ ? "Will" : "Won't") << " sync with word; bit length is " << ((control & 0x100) ? "short" : "long"));
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}
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void Chipset::DiskController::process_index_hole() {
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// Pulse the CIA flag input.
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//
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// TODO: rectify once drives do an actual index pulse, with length.
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cia_.set_flag_input(true);
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cia_.set_flag_input(false);
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// Resync word output. Experimental!!
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bit_count_ = 0;
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}
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void Chipset::DiskController::set_mtr_sel_side_dir_step(uint8_t value) {
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// b7: /MTR
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// b6: /SEL3
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// b5: /SEL2
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// b4: /SEL1
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// b3: /SEL0
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// b2: /SIDE
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// b1: DIR
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// b0: /STEP
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// Select active drive.
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set_drive(((value >> 3) & 0x0f) ^ 0x0f);
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// "[The MTR] signal is nonstandard on the Amiga system.
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// Each drive will latch the motor signal at the time its
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// select signal turns on." — The Hardware Reference Manual.
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const auto difference = int(previous_select_ ^ value);
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previous_select_ = value;
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// Check for changes in the SEL line per drive.
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const bool motor_on = !(value & 0x80);
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const int side = (value & 0x04) ? 0 : 1;
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const bool did_step = difference & value & 0x01;
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const auto direction = Storage::Disk::HeadPosition(
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(value & 0x02) ? -1 : 1
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);
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for(int c = 0; c < 4; c++) {
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auto &drive = get_drive(size_t(c));
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const int select_mask = 0x08 << c;
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const bool is_selected = !(value & select_mask);
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// Both the motor state and the ID shifter are affected upon
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// changes in drive selection only.
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if(difference & select_mask) {
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// If transitioning to inactive, shift the drive ID value;
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// if transitioning to active, possibly reset the drive
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// ID and definitely latch the new motor state.
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if(!is_selected) {
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drive_ids_[c] <<= 1;
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LOG("Shifted drive ID shift register for drive " << +c << " to " << PADHEX(4) << std::bitset<16>{drive_ids_[c]});
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} else {
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// Motor transition on -> off => reload register.
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if(!motor_on && drive.get_motor_on()) {
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// NB:
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// 0xffff'ffff = 3.5" drive;
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// 0x5555'5555 = 5.25" drive;
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// 0x0000'0000 = no drive.
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drive_ids_[c] = 0xffff'ffff;
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LOG("Reloaded drive ID shift register for drive " << +c);
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}
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// Also latch the new motor state.
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drive.set_motor_on(motor_on);
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}
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}
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// Set the new side.
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drive.set_head(side);
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// Possibly step.
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if(did_step && is_selected) {
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LOG("Stepped drive " << +c << " by " << std::dec << +direction.as_int());
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drive.step(direction);
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}
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}
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}
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uint8_t Chipset::DiskController::get_rdy_trk0_wpro_chng() {
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// b5: /RDY
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// b4: /TRK0
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// b3: /WPRO
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// b2: /CHNG
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// My interpretation:
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//
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// RDY isn't RDY, it's a shift value as described above, combined with the motor state.
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// CHNG is what is normally RDY.
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const uint32_t combined_id =
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((previous_select_ & 0x40) ? 0 : drive_ids_[3]) |
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((previous_select_ & 0x20) ? 0 : drive_ids_[2]) |
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((previous_select_ & 0x10) ? 0 : drive_ids_[1]) |
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((previous_select_ & 0x08) ? 0 : drive_ids_[0]);
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auto &drive = get_drive();
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const uint8_t active_high =
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((combined_id & 0x8000) >> 10) |
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(drive.get_motor_on() ? 0x20 : 0x00) |
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(drive.get_is_ready() ? 0x00 : 0x04) |
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(drive.get_is_track_zero() ? 0x10 : 0x00) |
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(drive.get_is_read_only() ? 0x08 : 0x00);
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return ~active_high;
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}
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void Chipset::DiskController::set_activity_observer(Activity::Observer *observer) {
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for_all_drives([observer] (Storage::Disk::Drive &drive, size_t index) {
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drive.set_activity_observer(observer, "Drive " + std::to_string(index+1), true);
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});
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}
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bool Chipset::DiskController::insert(const std::shared_ptr<Storage::Disk::Disk> &disk, size_t drive) {
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if(drive >= 4) return false;
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get_drive(drive).set_disk(disk);
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return true;
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}
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bool Chipset::insert(const std::vector<std::shared_ptr<Storage::Disk::Disk>> &disks) {
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bool inserted = false;
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size_t target = 0;
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for(const auto &disk: disks) {
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inserted |= disk_controller_.insert(disk, target);
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++target;
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}
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return inserted;
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}
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// MARK: - Mouse.
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int Chipset::Mouse::get_number_of_buttons() {
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252
Machines/Amiga/Disk.cpp
Normal file
252
Machines/Amiga/Disk.cpp
Normal file
@ -0,0 +1,252 @@
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//
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// Disk.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 02/11/2021.
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// Copyright © 2021 Thomas Harte. All rights reserved.
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//
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#include "Chipset.hpp"
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#define LOG_PREFIX "[Disk] "
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#include "../../Outputs/Log.hpp"
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using namespace Amiga;
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// MARK: - Disk DMA.
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void Chipset::DiskDMA::enqueue(uint16_t value, bool matches_sync) {
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if(matches_sync) {
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// TODO: start buffering from the next word onwards if
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// syncing is enabled.
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}
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// LOG("In: " << buffer_write_);
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buffer_[buffer_write_ & 3] = value;
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if(buffer_write_ == buffer_read_ + 4) {
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++buffer_read_;
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}
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++buffer_write_;
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}
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void Chipset::DiskDMA::set_length(uint16_t value) {
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if(value == last_set_length_) {
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dma_enable_ = value & 0x8000;
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write_ = value & 0x4000;
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length_ = value & 0x3fff;
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buffer_read_ = buffer_write_ = 0;
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if(dma_enable_) {
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LOG("Disk DMA " << (write_ ? "write" : "read") << " of " << length_ << " to " << PADHEX(8) << pointer_[0]);
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}
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}
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last_set_length_ = value;
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}
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bool Chipset::DiskDMA::advance() {
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if(!dma_enable_) return false;
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if(!write_) {
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if(length_ && buffer_read_ != buffer_write_) {
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ram_[pointer_[0] & ram_mask_] = buffer_[buffer_read_ & 3];
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++pointer_[0];
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++buffer_read_;
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--length_;
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if(!length_) {
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chipset_.posit_interrupt(InterruptFlag::DiskBlock);
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}
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return true;
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}
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}
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return false;
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}
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// MARK: - Disk Controller.
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Chipset::DiskController::DiskController(Cycles clock_rate, Chipset &chipset, DiskDMA &disk_dma, CIAB &cia) :
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Storage::Disk::Controller(clock_rate),
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chipset_(chipset),
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disk_dma_(disk_dma),
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cia_(cia) {
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// Add four drives.
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for(int c = 0; c < 4; c++) {
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emplace_drive(clock_rate.as<int>(), 300, 2, Storage::Disk::Drive::ReadyType::IBMRDY);
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}
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}
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void Chipset::DiskController::process_input_bit(int value) {
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data_ = uint16_t((data_ << 1) | value);
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++bit_count_;
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const bool sync_matches = data_ == sync_word_;
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if(sync_matches) {
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chipset_.posit_interrupt(InterruptFlag::DiskSyncMatch);
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if(sync_with_word_) {
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bit_count_ = 0;
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}
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}
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if(!(bit_count_ & 15)) {
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disk_dma_.enqueue(data_, sync_matches);
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}
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}
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void Chipset::DiskController::set_sync_word(uint16_t value) {
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LOG("Set disk sync word to " << PADHEX(4) << value);
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sync_word_ = value;
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}
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void Chipset::DiskController::set_control(uint16_t control) {
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// b13 and b14: precompensation length specifier
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// b12: 0 => GCR precompensation; 1 => MFM.
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// b10: 1 => enable use of word sync; 0 => disable.
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// b9: 1 => sync on MSB (Disk II style, presumably?); 0 => don't.
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// b8: 1 => 2µs per bit; 0 => 4µs.
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sync_with_word_ = control & 0x400;
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Storage::Time bit_length;
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bit_length.length = 1;
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bit_length.clock_rate = (control & 0x100) ? 500000 : 250000;
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set_expected_bit_length(bit_length);
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LOG((sync_with_word_ ? "Will" : "Won't") << " sync with word; bit length is " << ((control & 0x100) ? "short" : "long"));
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}
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void Chipset::DiskController::process_index_hole() {
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// Pulse the CIA flag input.
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//
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// TODO: rectify once drives do an actual index pulse, with length.
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cia_.set_flag_input(true);
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cia_.set_flag_input(false);
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// Resync word output. Experimental!!
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bit_count_ = 0;
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}
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void Chipset::DiskController::set_mtr_sel_side_dir_step(uint8_t value) {
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// b7: /MTR
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// b6: /SEL3
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// b5: /SEL2
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// b4: /SEL1
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// b3: /SEL0
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// b2: /SIDE
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// b1: DIR
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// b0: /STEP
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// Select active drive.
|
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set_drive(((value >> 3) & 0x0f) ^ 0x0f);
|
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|
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// "[The MTR] signal is nonstandard on the Amiga system.
|
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// Each drive will latch the motor signal at the time its
|
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// select signal turns on." — The Hardware Reference Manual.
|
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const auto difference = int(previous_select_ ^ value);
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previous_select_ = value;
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// Check for changes in the SEL line per drive.
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const bool motor_on = !(value & 0x80);
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const int side = (value & 0x04) ? 0 : 1;
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const bool did_step = difference & value & 0x01;
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const auto direction = Storage::Disk::HeadPosition(
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(value & 0x02) ? -1 : 1
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);
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for(int c = 0; c < 4; c++) {
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auto &drive = get_drive(size_t(c));
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const int select_mask = 0x08 << c;
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const bool is_selected = !(value & select_mask);
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// Both the motor state and the ID shifter are affected upon
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// changes in drive selection only.
|
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if(difference & select_mask) {
|
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// If transitioning to inactive, shift the drive ID value;
|
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// if transitioning to active, possibly reset the drive
|
||||
// ID and definitely latch the new motor state.
|
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if(!is_selected) {
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drive_ids_[c] <<= 1;
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LOG("Shifted drive ID shift register for drive " << +c << " to " << PADHEX(4) << std::bitset<16>{drive_ids_[c]});
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} else {
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// Motor transition on -> off => reload register.
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if(!motor_on && drive.get_motor_on()) {
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// NB:
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// 0xffff'ffff = 3.5" drive;
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// 0x5555'5555 = 5.25" drive;
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// 0x0000'0000 = no drive.
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drive_ids_[c] = 0xffff'ffff;
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LOG("Reloaded drive ID shift register for drive " << +c);
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}
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// Also latch the new motor state.
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drive.set_motor_on(motor_on);
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}
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}
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// Set the new side.
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drive.set_head(side);
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// Possibly step.
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if(did_step && is_selected) {
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LOG("Stepped drive " << +c << " by " << std::dec << +direction.as_int());
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drive.step(direction);
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}
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}
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}
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uint8_t Chipset::DiskController::get_rdy_trk0_wpro_chng() {
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// b5: /RDY
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// b4: /TRK0
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// b3: /WPRO
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// b2: /CHNG
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// My interpretation:
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//
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// RDY isn't RDY, it's a shift value as described above, combined with the motor state.
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// CHNG is what is normally RDY.
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const uint32_t combined_id =
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((previous_select_ & 0x40) ? 0 : drive_ids_[3]) |
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((previous_select_ & 0x20) ? 0 : drive_ids_[2]) |
|
||||
((previous_select_ & 0x10) ? 0 : drive_ids_[1]) |
|
||||
((previous_select_ & 0x08) ? 0 : drive_ids_[0]);
|
||||
|
||||
auto &drive = get_drive();
|
||||
const uint8_t active_high =
|
||||
((combined_id & 0x8000) >> 10) |
|
||||
(drive.get_motor_on() ? 0x20 : 0x00) |
|
||||
(drive.get_is_ready() ? 0x00 : 0x04) |
|
||||
(drive.get_is_track_zero() ? 0x10 : 0x00) |
|
||||
(drive.get_is_read_only() ? 0x08 : 0x00);
|
||||
|
||||
return ~active_high;
|
||||
}
|
||||
|
||||
void Chipset::DiskController::set_activity_observer(Activity::Observer *observer) {
|
||||
for_all_drives([observer] (Storage::Disk::Drive &drive, size_t index) {
|
||||
drive.set_activity_observer(observer, "Drive " + std::to_string(index+1), true);
|
||||
});
|
||||
}
|
||||
|
||||
bool Chipset::DiskController::insert(const std::shared_ptr<Storage::Disk::Disk> &disk, size_t drive) {
|
||||
if(drive >= 4) return false;
|
||||
get_drive(drive).set_disk(disk);
|
||||
return true;
|
||||
}
|
||||
|
||||
bool Chipset::insert(const std::vector<std::shared_ptr<Storage::Disk::Disk>> &disks) {
|
||||
bool inserted = false;
|
||||
|
||||
size_t target = 0;
|
||||
for(const auto &disk: disks) {
|
||||
inserted |= disk_controller_.insert(disk, target);
|
||||
++target;
|
||||
}
|
||||
|
||||
return inserted;
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user