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Introduces storage for various bus inputs.

This commit is contained in:
Thomas Harte 2019-04-29 19:22:05 -04:00
parent bc00856c05
commit 3da1b3bf9b
2 changed files with 29 additions and 7 deletions

View File

@ -217,26 +217,41 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform = false> cla
void run_for(HalfCycles duration);
using State = ProcessorState;
/// @returns The current processor state.
State get_state();
/// Sets the processor to the supplied state.
void set_state(const State &);
/// Sets the DTack line — @c true for active, @c false for inactive.
void set_dtack(bool);
inline void set_dtack(bool dtack) {
dtack_ = dtack;
}
/// Sets the VPA (valid peripheral address) line — @c true for active, @c false for inactive.
void set_is_peripheral_address(bool);
inline void set_is_peripheral_address(bool is_peripheral_address) {
is_peripheral_address_ = is_peripheral_address;
}
/// Sets the bus error line — @c true for active, @c false for inactive.
void set_bus_error(bool);
void set_bus_error(bool bus_error) {
bus_error_ = bus_error;
}
/// Sets the interrupt lines, IPL0, IPL1 and IPL2.
void set_interrupt_level(int);
void set_interrupt_level(int interrupt_level) {
bus_interrupt_level_ = interrupt_level;
}
/// Sets the bus request line.
void set_bus_request(bool);
void set_bus_request(bool bus_request) {
bus_request_ = bus_request;
}
/// Sets the bus acknowledge line.
void set_bus_acknowledge(bool);
void set_bus_acknowledge(bool bus_acknowledge) {
bus_acknowledge_ = bus_acknowledge;
}
private:
T &bus_handler_;

View File

@ -22,7 +22,6 @@ class ProcessorStorage {
// are copied into/out of address_[7] upon mode switches.
RegisterPair32 prefetch_queue_; // Each word will go into the low part of the word, then proceed upward.
bool dtack_ = true;
// Various status bits.
int is_supervisor_;
@ -34,6 +33,14 @@ class ProcessorStorage {
uint_fast32_t negative_flag_; // The negative flag is set if this value is non-zero.
uint_fast32_t trace_flag_; // The trace flag is set if this value is non-zero.
// Bus inputs.
int bus_interrupt_level_ = 0;
bool dtack_ = false;
bool is_peripheral_address_ = false;
bool bus_error_ = false;
bool bus_request_ = false;
bool bus_acknowledge_ = false;
// Generic sources and targets for memory operations;
// by convention: [0] = source, [1] = destination.
RegisterPair32 effective_address_[2];