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Introduces storage for various bus inputs.
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@ -217,26 +217,41 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform = false> cla
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void run_for(HalfCycles duration);
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using State = ProcessorState;
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/// @returns The current processor state.
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State get_state();
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/// Sets the processor to the supplied state.
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void set_state(const State &);
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/// Sets the DTack line — @c true for active, @c false for inactive.
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void set_dtack(bool);
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inline void set_dtack(bool dtack) {
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dtack_ = dtack;
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}
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/// Sets the VPA (valid peripheral address) line — @c true for active, @c false for inactive.
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void set_is_peripheral_address(bool);
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inline void set_is_peripheral_address(bool is_peripheral_address) {
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is_peripheral_address_ = is_peripheral_address;
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}
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/// Sets the bus error line — @c true for active, @c false for inactive.
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void set_bus_error(bool);
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void set_bus_error(bool bus_error) {
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bus_error_ = bus_error;
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}
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/// Sets the interrupt lines, IPL0, IPL1 and IPL2.
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void set_interrupt_level(int);
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void set_interrupt_level(int interrupt_level) {
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bus_interrupt_level_ = interrupt_level;
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}
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/// Sets the bus request line.
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void set_bus_request(bool);
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void set_bus_request(bool bus_request) {
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bus_request_ = bus_request;
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}
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/// Sets the bus acknowledge line.
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void set_bus_acknowledge(bool);
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void set_bus_acknowledge(bool bus_acknowledge) {
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bus_acknowledge_ = bus_acknowledge;
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}
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private:
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T &bus_handler_;
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@ -22,7 +22,6 @@ class ProcessorStorage {
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// are copied into/out of address_[7] upon mode switches.
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RegisterPair32 prefetch_queue_; // Each word will go into the low part of the word, then proceed upward.
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bool dtack_ = true;
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// Various status bits.
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int is_supervisor_;
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@ -34,6 +33,14 @@ class ProcessorStorage {
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uint_fast32_t negative_flag_; // The negative flag is set if this value is non-zero.
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uint_fast32_t trace_flag_; // The trace flag is set if this value is non-zero.
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// Bus inputs.
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int bus_interrupt_level_ = 0;
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bool dtack_ = false;
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bool is_peripheral_address_ = false;
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bool bus_error_ = false;
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bool bus_request_ = false;
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bool bus_acknowledge_ = false;
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// Generic sources and targets for memory operations;
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// by convention: [0] = source, [1] = destination.
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RegisterPair32 effective_address_[2];
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