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mirror of https://github.com/TomHarte/CLK.git synced 2025-04-22 09:37:21 +00:00

Double nominal clock, to hit normative values.

This commit is contained in:
Thomas Harte 2024-12-14 11:55:10 -05:00
parent 589903c43c
commit 3e93004db6
2 changed files with 16 additions and 9 deletions

View File

@ -113,11 +113,11 @@ public:
timers_(interrupts_),
video_(map_, interrupts_)
{
// PAL: 8867240 divided by 5 or 4?
// NTSC: 7159090?
// PAL: 17,734,480 Mhz divided by 5 or 4?
// NTSC: 14,318,180 Mhz
// i.e. colour subcarriers multiplied by two?
set_clock_rate(8867240); // TODO.
set_clock_rate(17'734'480);
const auto kernel = ROM::Name::Plus4KernelPALv5;
const auto basic = ROM::Name::Plus4BASIC;

View File

@ -121,9 +121,9 @@ public:
const bool is_long_cycle = single_clock_ || refresh_;
if(is_ntsc_) {
return is_long_cycle ? Cycles(8) : Cycles(4);
return is_long_cycle ? Cycles(16) : Cycles(8);
} else {
return is_long_cycle ? Cycles(10) : Cycles(5);
return is_long_cycle ? Cycles(20) : Cycles(10);
}
}
@ -141,11 +141,18 @@ public:
void run_for(Cycles cycles) {
// Timing:
//
// 456 cycles/line;
// if in PAL mode, divide input clock by 1.25 (?);
// see page 34 of plus4_tech.pdf for event times.
// Input clock is at 17.7Mhz PAL or 14.38Mhz NTSC. i.e. each is four times the colour subcarrier.
//
// In PAL mode, divide by 5 and multiply by 2 to get the internal pixel clock.
//
// In NTSC mode just dividing by 2 would do to get the pixel clock but in practice that's implemented as
// a divide by 4 and a multiply by 2 to keep it similar to the PAL code.
//
// That gives close enough to 456 pixel clocks per line in both systems so the TED just rolls with that.
subcycles_ += cycles * 4;
// See page 34 of plus4_tech.pdf for event times.
subcycles_ += cycles * 2;
auto ticks_remaining = subcycles_.divide(is_ntsc_ ? Cycles(4) : Cycles(5)).as<int>();
while(ticks_remaining) {
//