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https://github.com/TomHarte/CLK.git
synced 2024-06-29 00:29:34 +00:00
Breaks video output while attempting to pull it into the main loop.
This commit is contained in:
Thomas Harte
parent
b6bf4d73ad
commit
402eab10f8
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@ -126,6 +126,89 @@ bool Chipset::Copper::advance(uint16_t position) {
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return true;
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}
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template <int cycle> void Chipset::output() {
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// Hardware stop is at 0x18;
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// 12/64 * 227 = 42.5625
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//
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// "However, horizontal blanking actually limits the displayable
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// video to 368 low resolution pixel"
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//
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// => 184 windows out of 227 are visible, which concurs.
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//
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// A complete from-thin-air guess:
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//
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// 7 cycles blank;
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// 17 cycles sync;
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// 3 cycles blank;
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// 9 cycles colour burst;
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// 7 cycles blank.
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constexpr int blank1 = 7;
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constexpr int sync = 17 + blank1;
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constexpr int blank2 = 3 + sync;
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constexpr int burst = 9 + blank2;
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constexpr int blank3 = 7 + burst;
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static_assert(blank3 == 43);
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#define LINK(location, action, length) \
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if(cycle == (location)) { \
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crt_.action((length) * 4); \
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}
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if(y_ < vertical_blank_height_) {
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// Put three lines of sync at the centre of the vertical blank period.
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// Offset by half a line if interlaced and on an odd frame.
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const int midline = vertical_blank_height_ >> 1;
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if(frame_height_ & 1) {
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if(y_ < midline - 1 || y_ > midline + 2) {
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LINK(blank1, output_blank, blank1);
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LINK(sync, output_sync, sync - blank1);
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LINK(line_length_ - 1, output_blank, line_length_ - 1 - sync);
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} else if(y_ == midline - 1) {
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LINK(113, output_blank, 113);
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LINK(line_length_ - 1, output_sync, line_length_ - 1 - 113);
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} else if(y_ == midline + 2) {
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LINK(113, output_sync, 113);
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LINK(line_length_ - 1, output_blank, line_length_ - 1 - 113);
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} else {
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LINK(blank1, output_sync, blank1);
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LINK(sync, output_blank, sync - blank1);
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LINK(line_length_ - 1, output_sync, line_length_ - 1 - sync);
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}
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} else {
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if(y_ < midline - 1 || y_ > midline + 1) {
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LINK(blank1, output_blank, blank1);
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LINK(sync, output_sync, sync - blank1);
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LINK(line_length_ - 1, output_blank, line_length_ - 1 - sync);
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} else {
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LINK(blank1, output_sync, blank1);
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LINK(sync, output_blank, sync - blank1);
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LINK(line_length_ - 1, output_sync, line_length_ - 1 - sync);
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}
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}
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} else {
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// Output the correct sequence of blanks, syncs and burst atomically.
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LINK(blank1, output_blank, blank1);
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LINK(sync, output_sync, sync - blank1);
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LINK(blank2, output_blank, blank2 - sync);
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LINK(burst, output_default_colour_burst, burst - blank2); // TODO: only if colour enabled.
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LINK(blank3, output_blank, blank3 - burst);
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// Output colour 0 to fill the rest of the line; Kickstart uses this
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// colour to post the error code. TODO: actual pixels, etc.
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if(cycle == line_length_ - 1) {
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uint16_t *const pixels = reinterpret_cast<uint16_t *>(crt_.begin_data(1));
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if(pixels) {
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*pixels = palette_[0];
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}
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crt_.output_data((cycle - blank3) * 4, 1);
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}
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}
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#undef LINK
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}
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template <int cycle, bool stop_if_cpu> bool Chipset::perform_cycle() {
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// TODO: actual CPU scheduling.
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if constexpr (stop_if_cpu) {
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@ -169,8 +252,7 @@ template <bool stop_on_cpu> Chipset::Changes Chipset::run(HalfCycles length) {
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// Update raster position, spooling out graphics.
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while(pixels_remaining) {
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// Determine number of pixels left on this line.
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int line_pixels = std::min(pixels_remaining, line_length_ - line_cycle_);
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pixels_remaining -= line_pixels;
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int line_pixels = std::min(pixels_remaining, (line_length_ * 4) - line_cycle_);
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//
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// Run DMA scheduler.
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@ -187,10 +269,12 @@ template <bool stop_on_cpu> Chipset::Changes Chipset::run(HalfCycles length) {
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// Advance to window boundary.
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const int distance_to_boundary = ((line_cycle_ - 1) & 3) ^ 3;
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line_pixels -= distance_to_boundary;
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pixels_remaining -= distance_to_boundary;
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line_cycle_ += distance_to_boundary;
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#define C(x) \
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case x: \
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assert(!(line_cycle_&3)); \
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if constexpr(stop_on_cpu) {\
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if(perform_cycle<x, stop_on_cpu>()) {\
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break;\
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@ -198,8 +282,10 @@ template <bool stop_on_cpu> Chipset::Changes Chipset::run(HalfCycles length) {
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} else {\
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perform_cycle<x, stop_on_cpu>(); \
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} \
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output<x>(); \
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if((line_cycle_ >> 2) == final_slot) break; \
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line_cycle_ += 4;
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line_cycle_ += 4; \
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pixels_remaining -= 4;
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#define C10(x) C(x); C(x+1); C(x+2); C(x+3); C(x+4); C(x+5); C(x+6); C(x+7); C(x+8); C(x+9);
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switch(line_cycle_ >> 2) {
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@ -215,95 +301,9 @@ template <bool stop_on_cpu> Chipset::Changes Chipset::run(HalfCycles length) {
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}
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#undef C
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// Update per the possibility that the above ended early.
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final_slot = line_cycle_ >> 2;
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int slot = line_cycle_ >> 2;
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//
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// Output video signal as implied by whatever happened above.
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//
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// Hardware stop is at 0x18;
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// 12/64 * 227 = 42.5625
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//
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// "However, horizontal blanking actually limits the displayable
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// video to 368 low resolution pixel"
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//
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// => 184 windows out of 227 are visible, which concurs.
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//
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// A complete from-thin-air guess:
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//
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// 7 cycles blank;
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// 17 cycles sync;
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// 3 cycles blank;
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// 9 cycles colour burst;
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// 7 cycles blank.
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constexpr int blank1 = 7;
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constexpr int sync = 17 + blank1;
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constexpr int blank2 = 3 + sync;
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constexpr int burst = 9 + blank2;
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constexpr int blank3 = 7 + burst;
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static_assert(blank3 == 43);
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#define LINK(location, action, length) \
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if(slot < (location) && final_slot >= (location)) { \
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crt_.action((length) * 4); \
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}
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if(y_ < vertical_blank_height_) {
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// Put three lines of sync at the centre of the vertical blank period.
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// TODO: offset by half a line if interlaced and on an odd frame.
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const int midline = vertical_blank_height_ >> 1;
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if(frame_height_ & 1) {
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if(y_ < midline - 1 || y_ > midline + 2) {
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LINK(blank1, output_blank, blank1);
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LINK(sync, output_sync, sync - blank1);
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LINK(line_length_, output_blank, line_length_ - sync);
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} else if(y_ == midline - 1) {
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LINK(113, output_blank, 113);
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LINK(line_length_, output_sync, line_length_ - 113);
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} else if(y_ == midline + 2) {
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LINK(113, output_sync, 113);
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LINK(line_length_, output_blank, line_length_ - 113);
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} else {
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LINK(blank1, output_sync, blank1);
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LINK(sync, output_blank, sync - blank1);
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LINK(line_length_, output_sync, line_length_ - sync);
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}
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} else {
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if(y_ < midline - 1 || y_ > midline + 1) {
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LINK(blank1, output_blank, blank1);
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LINK(sync, output_sync, sync - blank1);
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LINK(line_length_, output_blank, line_length_ - sync);
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} else {
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LINK(blank1, output_sync, blank1);
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LINK(sync, output_blank, sync - blank1);
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LINK(line_length_, output_sync, line_length_ - sync);
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}
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}
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} else {
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// Output the correct sequence of blanks, syncs and burst atomically.
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LINK(blank1, output_blank, blank1);
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LINK(sync, output_sync, sync - blank1);
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LINK(blank2, output_blank, blank2 - sync);
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LINK(burst, output_default_colour_burst, burst - blank2); // TODO: only if colour enabled.
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LINK(blank3, output_blank, blank3 - burst);
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// Output colour 0 to fill the rest of the line; Kickstart uses this
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// colour to post the error code. TODO: actual pixels, etc.
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if(line_cycle_ == line_length_) {
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uint16_t *const pixels = reinterpret_cast<uint16_t *>(crt_.begin_data(1));
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if(pixels) {
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*pixels = palette_[0];
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}
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crt_.output_data(line_length_ - blank3 * 4, 1);
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}
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}
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// Advance intraline counter and possibly ripple upwards into
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// lines and fields.
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if(line_cycle_ == line_length_) {
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if(line_cycle_ == (line_length_ * 4)) {
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++changes.hsyncs;
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line_cycle_ = 0;
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@ -321,7 +321,6 @@ template <bool stop_on_cpu> Chipset::Changes Chipset::run(HalfCycles length) {
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}
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}
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}
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#undef LINK
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changes.interrupt_level = interrupt_level_;
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changes.duration = length;
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@ -67,6 +67,7 @@ class Chipset {
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template <bool stop_on_cpu> Changes run(HalfCycles duration = HalfCycles());
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template <int cycle, bool stop_if_cpu> bool perform_cycle();
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template <int cycle> void output();
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// MARK: - DMA Control, Scheduler and Blitter.
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@ -85,7 +86,7 @@ class Chipset {
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// MARK: - Raster.
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int line_cycle_ = 0, y_ = 0;
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int line_length_ = 227 * 4;
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int line_length_ = 227;
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int frame_height_ = 312;
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int vertical_blank_height_ = 29;
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