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Increases likelihood of 68000 Program
offset-size assumptions being met.
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@ -23,6 +23,16 @@ class ProcessorStorage {
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RegisterPair32 prefetch_queue_; // Each word will go into the low part of the word, then proceed upward.
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// Generic sources and targets for memory operations;
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// by convention: effective_address_[0] = source, [1] = destination.
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//
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// These, and the various register contents above, should be kept
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// close to the top of this class so that small-integer offsets can be
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// used in instances of Program (see below).
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RegisterPair32 effective_address_[2];
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RegisterPair32 source_bus_data_;
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RegisterPair32 destination_bus_data_;
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enum class ExecutionState {
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/// The normal mode, this means the 68000 is expending processing effort.
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Executing,
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@ -72,12 +82,6 @@ class ProcessorStorage {
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int accepted_interrupt_level_ = 0;
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bool is_starting_interrupt_ = false;
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// Generic sources and targets for memory operations;
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// by convention: [0] = source, [1] = destination.
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RegisterPair32 effective_address_[2];
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RegisterPair32 source_bus_data_;
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RegisterPair32 destination_bus_data_;
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HalfCycles half_cycles_left_to_run_;
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HalfCycles e_clock_phase_;
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@ -383,11 +387,13 @@ class ProcessorStorage {
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void set_source(ProcessorStorage &storage, RegisterPair32 *target) {
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source_offset = decltype(source_offset)(reinterpret_cast<uint8_t *>(target) - reinterpret_cast<uint8_t *>(&storage));
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// Test that destination_offset could be stored fully within the integer size provided for source_offset.
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assert(source_offset == (reinterpret_cast<uint8_t *>(target) - reinterpret_cast<uint8_t *>(&storage)));
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}
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void set_destination(ProcessorStorage &storage, RegisterPair32 *target) {
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destination_offset = decltype(destination_offset)(reinterpret_cast<uint8_t *>(target) - reinterpret_cast<uint8_t *>(&storage));
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// Test that destination_offset could be stored fully within the integer size provided for destination_offset.
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assert(destination_offset == (reinterpret_cast<uint8_t *>(target) - reinterpret_cast<uint8_t *>(&storage)));
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}
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