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https://github.com/TomHarte/CLK.git
synced 2025-01-26 15:32:04 +00:00
Unify DMA interface.
This commit is contained in:
Thomas Harte
parent
0bcb17985b
commit
4265455c31
@ -25,135 +25,73 @@ enum class AccessResult {
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class i8237 {
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public:
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void flip_flop_reset() {
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printf("DMA: Flip flop reset\n");
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next_access_low_ = true;
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}
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void mask_reset() {
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printf("DMA: Mask reset\n");
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for(auto &channel : channels_) {
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channel.mask = false;
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}
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}
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void master_reset() {
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printf("DMA: Master reset\n");
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flip_flop_reset();
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for(auto &channel : channels_) {
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channel.mask = true;
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channel.transfer_complete = false;
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channel.request = false;
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}
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// This is a bit of a hack; DMA channel 0 is supposed to be linked to the PIT,
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// performing DRAM refresh. It isn't yet. So hack this, and hack that.
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channels_[0].transfer_complete = true;
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}
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//
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// CPU-facing interface.
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//
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template <int address>
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void write(uint8_t value) {
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printf("DMA: Write %02x to %d\n", value, address);
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constexpr int channel = (address >> 1) & 3;
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constexpr bool is_count = address & 1;
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next_access_low_ ^= true;
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if(next_access_low_) {
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if constexpr (is_count) {
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channels_[channel].count.halves.high = value;
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} else {
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channels_[channel].address.halves.high = value;
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}
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} else {
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if constexpr (is_count) {
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channels_[channel].count.halves.low = value;
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} else {
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channels_[channel].address.halves.low = value;
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}
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switch(address) {
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default: {
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constexpr int channel = (address >> 1) & 3;
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constexpr bool is_count = address & 1;
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next_access_low_ ^= true;
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if(next_access_low_) {
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if constexpr (is_count) {
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channels_[channel].count.halves.high = value;
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} else {
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channels_[channel].address.halves.high = value;
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}
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} else {
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if constexpr (is_count) {
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channels_[channel].count.halves.low = value;
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} else {
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channels_[channel].address.halves.low = value;
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}
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}
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} break;
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case 0x8: set_command(value); break;
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case 0x9: set_reset_request(value); break;
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case 0xa: set_reset_mask(value); break;
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case 0xb: set_mode(value); break;
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case 0xc: flip_flop_reset(); break;
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case 0xd: master_reset(); break;
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case 0xe: mask_reset(); break;
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case 0xf: set_mask(value); break;
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}
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}
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template <int address>
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uint8_t read() {
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printf("DMA: Read %d\n", address);
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constexpr int channel = (address >> 1) & 3;
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constexpr bool is_count = address & 1;
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switch(address) {
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default: {
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constexpr int channel = (address >> 1) & 3;
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constexpr bool is_count = address & 1;
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next_access_low_ ^= true;
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if(next_access_low_) {
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if constexpr (is_count) {
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return channels_[channel].count.halves.high;
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} else {
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return channels_[channel].address.halves.high;
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}
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} else {
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if constexpr (is_count) {
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return channels_[channel].count.halves.low;
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} else {
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return channels_[channel].address.halves.low;
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}
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next_access_low_ ^= true;
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if(next_access_low_) {
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if constexpr (is_count) {
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return channels_[channel].count.halves.high;
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} else {
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return channels_[channel].address.halves.high;
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}
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} else {
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if constexpr (is_count) {
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return channels_[channel].count.halves.low;
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} else {
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return channels_[channel].address.halves.low;
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}
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}
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} break;
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case 0x8: return status(); break;
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case 0xd: return temporary_register(); break;
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}
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}
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void set_reset_mask(uint8_t value) {
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printf("DMA: Set/reset mask %02x\n", value);
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channels_[value & 3].mask = value & 4;
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}
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void set_reset_request(uint8_t value) {
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printf("DMA: Set/reset request %02x\n", value);
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channels_[value & 3].request = value & 4;
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}
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void set_mask(uint8_t value) {
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printf("DMA: Set mask %02x\n", value);
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channels_[0].mask = value & 1;
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channels_[1].mask = value & 2;
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channels_[2].mask = value & 4;
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channels_[3].mask = value & 8;
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}
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void set_mode(uint8_t value) {
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printf("DMA: Set mode %02x\n", value);
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channels_[value & 3].transfer = Channel::Transfer((value >> 2) & 3);
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channels_[value & 3].autoinitialise = value & 0x10;
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channels_[value & 3].address_decrement = value & 0x20;
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channels_[value & 3].mode = Channel::Mode(value >> 6);
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}
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void set_command(uint8_t value) {
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printf("DMA: Set command %02x\n", value);
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enable_memory_to_memory_ = value & 0x01;
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enable_channel0_address_hold_ = value & 0x02;
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enable_controller_ = value & 0x04;
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compressed_timing_ = value & 0x08;
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rotating_priority_ = value & 0x10;
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extended_write_selection_ = value & 0x20;
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dreq_active_low_ = value & 0x40;
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dack_sense_active_high_ = value & 0x80;
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}
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uint8_t status() {
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const uint8_t result =
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(channels_[0].transfer_complete ? 0x01 : 0x00) |
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(channels_[1].transfer_complete ? 0x02 : 0x00) |
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(channels_[2].transfer_complete ? 0x04 : 0x00) |
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(channels_[3].transfer_complete ? 0x08 : 0x00) |
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(channels_[0].request ? 0x10 : 0x00) |
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(channels_[1].request ? 0x20 : 0x00) |
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(channels_[2].request ? 0x40 : 0x00) |
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(channels_[3].request ? 0x80 : 0x00);
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for(auto &channel : channels_) {
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channel.transfer_complete = false;
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}
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printf("DMA: status is %02x\n", result);
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return result;
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}
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//
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// Interface for reading/writing via DMA.
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//
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@ -192,6 +130,96 @@ class i8237 {
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}
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private:
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uint8_t status() {
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const uint8_t result =
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(channels_[0].transfer_complete ? 0x01 : 0x00) |
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(channels_[1].transfer_complete ? 0x02 : 0x00) |
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(channels_[2].transfer_complete ? 0x04 : 0x00) |
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(channels_[3].transfer_complete ? 0x08 : 0x00) |
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(channels_[0].request ? 0x10 : 0x00) |
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(channels_[1].request ? 0x20 : 0x00) |
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(channels_[2].request ? 0x40 : 0x00) |
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(channels_[3].request ? 0x80 : 0x00);
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for(auto &channel : channels_) {
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channel.transfer_complete = false;
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}
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printf("DMA: status is %02x\n", result);
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return result;
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}
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uint8_t temporary_register() const {
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// Not actually implemented, so...
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return 0xff;
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}
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void flip_flop_reset() {
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printf("DMA: Flip flop reset\n");
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next_access_low_ = true;
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}
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void mask_reset() {
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printf("DMA: Mask reset\n");
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for(auto &channel : channels_) {
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channel.mask = false;
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}
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}
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void master_reset() {
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printf("DMA: Master reset\n");
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flip_flop_reset();
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for(auto &channel : channels_) {
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channel.mask = true;
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channel.transfer_complete = false;
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channel.request = false;
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}
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// This is a bit of a hack; DMA channel 0 is supposed to be linked to the PIT,
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// performing DRAM refresh. It isn't yet. So hack this, and hack that.
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channels_[0].transfer_complete = true;
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}
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void set_reset_mask(uint8_t value) {
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printf("DMA: Set/reset mask %02x\n", value);
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channels_[value & 3].mask = value & 4;
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}
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void set_reset_request(uint8_t value) {
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printf("DMA: Set/reset request %02x\n", value);
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channels_[value & 3].request = value & 4;
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}
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void set_mask(uint8_t value) {
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printf("DMA: Set mask %02x\n", value);
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channels_[0].mask = value & 1;
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channels_[1].mask = value & 2;
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channels_[2].mask = value & 4;
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channels_[3].mask = value & 8;
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}
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void set_mode(uint8_t value) {
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printf("DMA: Set mode %02x\n", value);
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channels_[value & 3].transfer = Channel::Transfer((value >> 2) & 3);
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channels_[value & 3].autoinitialise = value & 0x10;
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channels_[value & 3].address_decrement = value & 0x20;
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channels_[value & 3].mode = Channel::Mode(value >> 6);
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}
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void set_command(uint8_t value) {
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printf("DMA: Set command %02x\n", value);
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enable_memory_to_memory_ = value & 0x01;
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enable_channel0_address_hold_ = value & 0x02;
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enable_controller_ = value & 0x04;
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compressed_timing_ = value & 0x08;
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rotating_priority_ = value & 0x10;
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extended_write_selection_ = value & 0x20;
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dreq_active_low_ = value & 0x40;
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dack_sense_active_high_ = value & 0x80;
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}
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// Low/high byte latch.
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bool next_access_low_ = true;
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@ -806,22 +806,22 @@ class IO {
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printf("TODO: NMIs %s\n", (value & 0x80) ? "masked" : "unmasked");
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break;
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case 0x0000: dma_.controller.write<0>(uint8_t(value)); break;
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case 0x0001: dma_.controller.write<1>(uint8_t(value)); break;
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case 0x0002: dma_.controller.write<2>(uint8_t(value)); break;
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case 0x0003: dma_.controller.write<3>(uint8_t(value)); break;
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case 0x0004: dma_.controller.write<4>(uint8_t(value)); break;
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case 0x0005: dma_.controller.write<5>(uint8_t(value)); break;
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case 0x0006: dma_.controller.write<6>(uint8_t(value)); break;
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case 0x0007: dma_.controller.write<7>(uint8_t(value)); break;
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case 0x0008: dma_.controller.set_command(uint8_t(value)); break;
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case 0x0009: dma_.controller.set_reset_request(uint8_t(value)); break;
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case 0x000a: dma_.controller.set_reset_mask(uint8_t(value)); break;
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case 0x000b: dma_.controller.set_mode(uint8_t(value)); break;
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case 0x000c: dma_.controller.flip_flop_reset(); break;
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case 0x000d: dma_.controller.master_reset(); break;
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case 0x000e: dma_.controller.mask_reset(); break;
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case 0x000f: dma_.controller.set_mask(uint8_t(value)); break;
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case 0x0000: dma_.controller.write<0x0>(uint8_t(value)); break;
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case 0x0001: dma_.controller.write<0x1>(uint8_t(value)); break;
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case 0x0002: dma_.controller.write<0x2>(uint8_t(value)); break;
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case 0x0003: dma_.controller.write<0x3>(uint8_t(value)); break;
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case 0x0004: dma_.controller.write<0x4>(uint8_t(value)); break;
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case 0x0005: dma_.controller.write<0x5>(uint8_t(value)); break;
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case 0x0006: dma_.controller.write<0x6>(uint8_t(value)); break;
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case 0x0007: dma_.controller.write<0x7>(uint8_t(value)); break;
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case 0x0008: dma_.controller.write<0x8>(uint8_t(value)); break;
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case 0x0009: dma_.controller.write<0x9>(uint8_t(value)); break;
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case 0x000a: dma_.controller.write<0xa>(uint8_t(value)); break;
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case 0x000b: dma_.controller.write<0xb>(uint8_t(value)); break;
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case 0x000c: dma_.controller.write<0xc>(uint8_t(value)); break;
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case 0x000d: dma_.controller.write<0xd>(uint8_t(value)); break;
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case 0x000e: dma_.controller.write<0xe>(uint8_t(value)); break;
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case 0x000f: dma_.controller.write<0xf>(uint8_t(value)); break;
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case 0x0020: pic_.write<0>(uint8_t(value)); break;
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case 0x0021: pic_.write<1>(uint8_t(value)); break;
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@ -910,21 +910,20 @@ class IO {
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printf("Unhandled in: %04x\n", port);
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break;
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case 0x0000: return dma_.controller.template read<0>();
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case 0x0001: return dma_.controller.template read<1>();
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case 0x0002: return dma_.controller.template read<2>();
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case 0x0003: return dma_.controller.template read<3>();
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case 0x0004: return dma_.controller.template read<4>();
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case 0x0005: return dma_.controller.template read<5>();
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case 0x0006: return dma_.controller.template read<6>();
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case 0x0007: return dma_.controller.template read<7>();
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case 0x0000: return dma_.controller.read<0x0>();
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case 0x0001: return dma_.controller.read<0x1>();
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case 0x0002: return dma_.controller.read<0x2>();
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case 0x0003: return dma_.controller.read<0x3>();
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case 0x0004: return dma_.controller.read<0x4>();
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case 0x0005: return dma_.controller.read<0x5>();
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case 0x0006: return dma_.controller.read<0x6>();
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case 0x0007: return dma_.controller.read<0x7>();
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case 0x0008: return dma_.controller.read<0x8>();
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case 0x000d: return dma_.controller.read<0xd>();
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case 0x0008: return dma_.controller.status();
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case 0x0009:
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case 0x000a: case 0x000b:
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case 0x0009: case 0x000b:
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case 0x000c: case 0x000f:
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printf("TODO: DMA read from %04x\n", port);
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// DMA area, but it doesn't respond.
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break;
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case 0x0020: return pic_.read<0>();
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