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Adjusted slightly as per Z80 change, and to pull everything internally declared into the Amstrad CPC namespace.
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@ -16,7 +16,7 @@
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#include "../../Storage/Tape/Tape.hpp"
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#include "../../Storage/Tape/Tape.hpp"
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using namespace AmstradCPC;
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namespace AmstradCPC {
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/*!
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/*!
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Models the CPC's interrupt timer. Inputs are vsync, hsync, interrupt acknowledge and reset, and its output
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Models the CPC's interrupt timer. Inputs are vsync, hsync, interrupt acknowledge and reset, and its output
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@ -478,10 +478,11 @@ class i8255PortHandler : public Intel::i8255::PortHandler {
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The actual Amstrad CPC implementation; tying the 8255, 6845 and AY to the Z80.
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The actual Amstrad CPC implementation; tying the 8255, 6845 and AY to the Z80.
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*/
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*/
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class ConcreteMachine:
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class ConcreteMachine:
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public CPU::Z80::Processor<ConcreteMachine>,
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public CPU::Z80::BusHandler,
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public Machine {
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public Machine {
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public:
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public:
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ConcreteMachine() :
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ConcreteMachine() :
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z80_(*this),
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crtc_counter_(HalfCycles(4)), // This starts the CRTC exactly out of phase with the memory accesses
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crtc_counter_(HalfCycles(4)), // This starts the CRTC exactly out of phase with the memory accesses
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crtc_(crtc_bus_handler_),
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crtc_(crtc_bus_handler_),
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crtc_bus_handler_(ram_, interrupt_timer_),
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crtc_bus_handler_(ram_, interrupt_timer_),
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@ -496,7 +497,7 @@ class ConcreteMachine:
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inline HalfCycles perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) {
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inline HalfCycles perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) {
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// Amstrad CPC timing scheme: assert WAIT for three out of four cycles
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// Amstrad CPC timing scheme: assert WAIT for three out of four cycles
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clock_offset_ = (clock_offset_ + cycle.length) & HalfCycles(7);
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clock_offset_ = (clock_offset_ + cycle.length) & HalfCycles(7);
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set_wait_line(clock_offset_ >= HalfCycles(2));
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z80_.set_wait_line(clock_offset_ >= HalfCycles(2));
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// Update the CRTC once every eight half cycles; aiming for half-cycle 4 as
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// Update the CRTC once every eight half cycles; aiming for half-cycle 4 as
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// per the initial seed to the crtc_counter_, but any time in the final four
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// per the initial seed to the crtc_counter_, but any time in the final four
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@ -505,7 +506,7 @@ class ConcreteMachine:
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crtc_counter_ += cycle.length;
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crtc_counter_ += cycle.length;
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int crtc_cycles = crtc_counter_.divide(HalfCycles(8)).as_int();
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int crtc_cycles = crtc_counter_.divide(HalfCycles(8)).as_int();
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if(crtc_cycles) crtc_.run_for(Cycles(1));
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if(crtc_cycles) crtc_.run_for(Cycles(1));
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set_interrupt_line(interrupt_timer_.get_request());
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z80_.set_interrupt_line(interrupt_timer_.get_request());
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// TODO (in the player, not here): adapt it to accept an input clock rate and
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// TODO (in the player, not here): adapt it to accept an input clock rate and
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// run_for as HalfCycles
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// run_for as HalfCycles
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@ -629,7 +630,7 @@ class ConcreteMachine:
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/// Wires virtual-dispatched CRTMachine run_for requests to the static Z80 method.
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/// Wires virtual-dispatched CRTMachine run_for requests to the static Z80 method.
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void run_for(const Cycles cycles) {
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void run_for(const Cycles cycles) {
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CPU::Z80::Processor<ConcreteMachine>::run_for(cycles);
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z80_.run_for(cycles);
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}
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}
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/// The ConfigurationTarget entry point; should configure this meachine as described by @c target.
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/// The ConfigurationTarget entry point; should configure this meachine as described by @c target.
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@ -674,6 +675,8 @@ class ConcreteMachine:
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}
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}
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private:
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private:
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CPU::Z80::Processor<ConcreteMachine> z80_;
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CRTCBusHandler crtc_bus_handler_;
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CRTCBusHandler crtc_bus_handler_;
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Motorola::CRTC::CRTC6845<CRTCBusHandler> crtc_;
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Motorola::CRTC::CRTC6845<CRTCBusHandler> crtc_;
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@ -697,7 +700,11 @@ class ConcreteMachine:
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KeyboardState key_state_;
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KeyboardState key_state_;
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};
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};
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}
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using namespace AmstradCPC;
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// See header; constructs and returns an instance of the Amstrad CPC.
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// See header; constructs and returns an instance of the Amstrad CPC.
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Machine *Machine::AmstradCPC() {
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Machine *Machine::AmstradCPC() {
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return new ConcreteMachine;
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return new AmstradCPC::ConcreteMachine;
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}
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}
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