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Starts to make incursions into MOVE[A].l.
This commit is contained in:
Thomas Harte
parent
d7c3d4ce52
commit
43532c8455
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@ -155,6 +155,12 @@ struct ProcessorStorageConstructor {
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step.microcycle.length = HalfCycles(3);
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step.microcycle.operation |= (read_full_words ? Microcycle::SelectWord : Microcycle::SelectByte) | (is_read ? Microcycle::Read : 0);
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if(access_pattern[1] == 'R') {
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step.action = Action::IncrementEffectiveAddress0;
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}
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if(access_pattern[1] == 'W') {
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step.action = Action::IncrementEffectiveAddress1;
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}
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steps.push_back(step);
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++address_iterator;
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@ -357,296 +363,309 @@ struct ProcessorStorageConstructor {
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// ... for no reason other than to make the switch below easy to read.
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const int both_modes =
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((source_mode == 7) ? (0x1000 | (source_register << 8)) : (source_mode << 8)) |
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((destination_mode == 7) ? (0x10 | destination_register) : destination_mode);
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((destination_mode == 7) ? (0x10 | destination_register) : destination_mode) |
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(is_long_word_access ? 0x10000 : 0);
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if(is_long_word_access) {
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continue;
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} else {
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switch(both_modes) {
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switch(both_modes) {
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//
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// Source = Dn or An
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//
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//
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// Source = Dn or An
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//
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case 0x0001: // MOVEA Dn, An
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case 0x0101: // MOVEA An, An
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operation = Operation::MOVEAw; // Substitute MOVEA for MOVE.
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case 0x0000: // MOVE Dn, Dn
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case 0x0100: // MOVE An, Dn
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op(Action::PerformOperation, seq("np"));
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case 0x10001: // MOVEA.l Dn, An
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case 0x10101: // MOVEA.l An, An
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case 0x00001: // MOVEA.w Dn, An
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case 0x00101: // MOVEA.w An, An
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operation = is_long_word_access ? Operation::MOVEAl : Operation::MOVEAw; // Substitute MOVEA for MOVE.
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case 0x10000: // MOVE.l Dn, Dn
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case 0x10100: // MOVE.l An, Dn
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case 0x00000: // MOVE.bw Dn, Dn
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case 0x00100: // MOVE.bw An, Dn
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op(Action::PerformOperation, seq("np"));
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op();
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break;
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case 0x0002: // MOVE Dn, (An)
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case 0x0102: // MOVE An, (An)
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case 0x0003: // MOVE Dn, (An)+
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case 0x0103: // MOVE An, (An)+
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op(is_byte_access ? Action::SetMoveFlagsb : Action::SetMoveFlagsw, seq("nw np", { &storage_.address_[destination_register].full }, !is_byte_access));
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if(destination_mode == 0x3) {
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op(int(is_byte_access ? Action::Increment1 : Action::Increment2) | MicroOp::DestinationMask);
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} else {
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op();
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break;
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}
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break;
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case 0x0002: // MOVE Dn, (An)
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case 0x0102: // MOVE An, (An)
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case 0x0003: // MOVE Dn, (An)+
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case 0x0103: // MOVE An, (An)+
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op(is_byte_access ? Action::SetMoveFlagsb : Action::SetMoveFlagsw, seq("nw np", { &storage_.address_[destination_register].full }, !is_byte_access));
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if(destination_mode == 0x3) {
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op(int(is_byte_access ? Action::Increment1 : Action::Increment2) | MicroOp::DestinationMask);
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} else {
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op();
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}
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break;
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case 0x0004: // MOVE Dn, -(An)
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case 0x0104: // MOVE An, -(An)
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op( int(is_byte_access ? Action::Decrement1 : Action::Decrement2) | MicroOp::DestinationMask,
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seq("np nw", { &storage_.address_[destination_register].full }, !is_byte_access));
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op(is_byte_access ? Action::SetMoveFlagsb : Action::SetMoveFlagsw);
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break;
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case 0x0004: // MOVE Dn, -(An)
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case 0x0104: // MOVE An, -(An)
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op( int(is_byte_access ? Action::Decrement1 : Action::Decrement2) | MicroOp::DestinationMask,
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seq("np nw", { &storage_.address_[destination_register].full }, !is_byte_access));
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op(is_byte_access ? Action::SetMoveFlagsb : Action::SetMoveFlagsw);
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break;
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case 0x0005: // MOVE Dn, (d16, An)
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case 0x0105: // MOVE An, (d16, An)
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// np nw np
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continue;
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case 0x0005: // MOVE Dn, (d16, An)
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case 0x0105: // MOVE An, (d16, An)
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// np nw np
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continue;
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case 0x0006: // MOVE Dn, (d8, An, Xn)
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case 0x0106: // MOVE An, (d8, An, Xn)
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// n np nw np
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continue;
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case 0x0006: // MOVE Dn, (d8, An, Xn)
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case 0x0106: // MOVE An, (d8, An, Xn)
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// n np nw np
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continue;
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case 0x0010: // MOVE Dn, (xxx).W
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case 0x0110: // MOVE An, (xxx).W
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// np nw np
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continue;
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case 0x0010: // MOVE Dn, (xxx).W
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case 0x0110: // MOVE An, (xxx).W
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// np nw np
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continue;
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case 0x0011: // MOVE Dn, (xxx).L
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case 0x0111: // MOVE An, (xxx).L
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// np np nw np
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continue;
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case 0x0011: // MOVE Dn, (xxx).L
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case 0x0111: // MOVE An, (xxx).L
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// np np nw np
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continue;
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//
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// Source = (An) or (An)+
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//
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//
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// Source = (An) or (An)+
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//
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case 0x00201: // MOVEA.w (An), An
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case 0x00301: // MOVEA.w (An)+, An
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operation = Operation::MOVEAw;
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case 0x00200: // MOVE.bw (An), Dn
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case 0x00300: // MOVE.bw (An)+, Dn
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op(Action::None, seq("nr np", { &storage_.address_[source_register].full }, !is_byte_access));
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if(source_mode == 0x3) {
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op(int(is_byte_access ? Action::Increment1 : Action::Increment2) | MicroOp::SourceMask);
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}
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op(Action::PerformOperation);
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break;
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case 0x0201: // MOVEA (An), An
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case 0x0301: // MOVEA (An)+, An
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operation = Operation::MOVEAw; // Substitute MOVEA for MOVE.
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case 0x0200: // MOVE (An), Dn
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case 0x0300: // MOVE (An)+, Dn
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op(Action::None, seq("nr np", { &storage_.address_[source_register].full }, !is_byte_access));
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if(source_mode == 0x3) {
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op(int(is_byte_access ? Action::Increment1 : Action::Increment2) | MicroOp::SourceMask);
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}
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op(Action::PerformOperation);
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break;
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case 0x10201: // MOVEA.l (An), An
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case 0x10301: // MOVEA.l (An)+, An
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operation = Operation::MOVEAl;
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case 0x10200: // MOVE.l (An), Dn
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case 0x10300: // MOVE.l (An)+, Dn
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op(Action::CopySourceToEffectiveAddress, seq("nR nr np"));
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if(source_mode == 0x3) {
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op(int(Action::Increment4) | MicroOp::SourceMask);
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}
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op(Action::PerformOperation);
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break;
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case 0x0202: // MOVE (An), (An)
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case 0x0302: // MOVE (An)+, (An)
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case 0x0203: // MOVE (An), (An)+
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case 0x0303: // MOVE (An)+, (An)+
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// nr nw np
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continue;
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case 0x0202: // MOVE (An), (An)
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case 0x0302: // MOVE (An)+, (An)
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case 0x0203: // MOVE (An), (An)+
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case 0x0303: // MOVE (An)+, (An)+
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// nr nw np
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continue;
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case 0x0204: // MOVE (An), -(An)
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case 0x0304: // MOVE (An)+, -(An)
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// nr np nw
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continue;
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case 0x0204: // MOVE (An), -(An)
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case 0x0304: // MOVE (An)+, -(An)
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// nr np nw
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continue;
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case 0x0205: // MOVE (An), (d16, An)
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case 0x0305: // MOVE (An)+, (d16, An)
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// nr np nw np
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continue;
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case 0x0205: // MOVE (An), (d16, An)
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case 0x0305: // MOVE (An)+, (d16, An)
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// nr np nw np
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continue;
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case 0x0206: // MOVE (An), (d8, An, Xn)
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case 0x0306: // MOVE (An)+, (d8, An, Xn)
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// nr n np nw np
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continue;
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case 0x0206: // MOVE (An), (d8, An, Xn)
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case 0x0306: // MOVE (An)+, (d8, An, Xn)
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// nr n np nw np
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continue;
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case 0x0210: // MOVE (An), (xxx).W
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case 0x0310: // MOVE (An)+, (xxx).W
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// nr np nw np
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continue;
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case 0x0210: // MOVE (An), (xxx).W
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case 0x0310: // MOVE (An)+, (xxx).W
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// nr np nw np
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continue;
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case 0x0211: // MOVE (An), (xxx).L
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case 0x0311: // MOVE (An)+, (xxx).L
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// nr np nw np np
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continue;
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case 0x0211: // MOVE (An), (xxx).L
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case 0x0311: // MOVE (An)+, (xxx).L
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// nr np nw np np
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continue;
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//
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// Source = -(An)
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//
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//
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// Source = -(An)
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//
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case 0x0401: // MOVEA -(An), An
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operation = Operation::MOVEAw; // Substitute MOVEA for MOVE.
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case 0x0400: // MOVE -(An), Dn
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op( int(is_byte_access ? Action::Decrement1 : Action::Decrement2) | MicroOp::SourceMask,
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seq("n nr np", { &storage_.address_[source_register].full }, !is_byte_access));
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op(Action::PerformOperation);
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break;
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case 0x0401: // MOVEA -(An), An
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operation = Operation::MOVEAw; // Substitute MOVEA for MOVE.
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case 0x0400: // MOVE -(An), Dn
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op( int(is_byte_access ? Action::Decrement1 : Action::Decrement2) | MicroOp::SourceMask,
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seq("n nr np", { &storage_.address_[source_register].full }, !is_byte_access));
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op(Action::PerformOperation);
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break;
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case 0x0402: // MOVE -(An), (An)
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case 0x0403: // MOVE -(An), (An)+
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// n nr nw np
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continue;
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case 0x0402: // MOVE -(An), (An)
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case 0x0403: // MOVE -(An), (An)+
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// n nr nw np
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continue;
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case 0x0404: // MOVE -(An), -(An)
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// n nr np nw
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continue;
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case 0x0404: // MOVE -(An), -(An)
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// n nr np nw
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continue;
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case 0x0405: // MOVE -(An), (d16, An)
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// n nr np nw
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continue;
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case 0x0405: // MOVE -(An), (d16, An)
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// n nr np nw
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continue;
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case 0x0406: // MOVE -(An), (d8, An, Xn)
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// n nr n np nw np
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continue;
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case 0x0406: // MOVE -(An), (d8, An, Xn)
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// n nr n np nw np
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continue;
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case 0x0410: // MOVE -(An), (xxx).W
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// n nr np nw np
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continue;
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case 0x0410: // MOVE -(An), (xxx).W
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// n nr np nw np
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continue;
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case 0x0411: // MOVE -(An), (xxx).L
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// n nr np nw np np
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continue;
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case 0x0411: // MOVE -(An), (xxx).L
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// n nr np nw np np
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continue;
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//
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// Source = (d16, An) or (d8, An, Xn)
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//
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//
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// Source = (d16, An) or (d8, An, Xn)
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//
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#define action_calc() int(source_mode == 0x05 ? Action::CalcD16An : Action::CalcD8AnXn)
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#define pseq(x) (source_mode == 0x06 ? "n" x : x)
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case 0x0501: // MOVE (d16, An), An
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case 0x0601: // MOVE (d8, An, Xn), An
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operation = Operation::MOVEAw;
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case 0x0500: // MOVE (d16, An), Dn
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case 0x0600: // MOVE (d8, An, Xn), Dn
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op(action_calc() | MicroOp::SourceMask, seq(pseq("np nr np"), { &storage_.effective_address_[0] }, !is_byte_access));
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op(Action::PerformOperation);
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break;
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case 0x0501: // MOVE (d16, An), An
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case 0x0601: // MOVE (d8, An, Xn), An
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operation = Operation::MOVEAw;
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case 0x0500: // MOVE (d16, An), Dn
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case 0x0600: // MOVE (d8, An, Xn), Dn
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op(action_calc() | MicroOp::SourceMask, seq(pseq("np nr np"), { &storage_.effective_address_[0] }, !is_byte_access));
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op(Action::PerformOperation);
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break;
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case 0x0502: // MOVE (d16, An), (An)
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case 0x0503: // MOVE (d16, An), (An)+
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case 0x0602: // MOVE (d8, An, Xn), (An)
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case 0x0603: // MOVE (d8, An, Xn), (An)+
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// np nr nw np
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// n np nr nw np
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continue;
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case 0x0502: // MOVE (d16, An), (An)
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case 0x0503: // MOVE (d16, An), (An)+
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case 0x0602: // MOVE (d8, An, Xn), (An)
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case 0x0603: // MOVE (d8, An, Xn), (An)+
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// np nr nw np
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// n np nr nw np
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continue;
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case 0x0504: // MOVE (d16, An), -(An)
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case 0x0604: // MOVE (d8, An, Xn), -(An)
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// np nr np nw
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// n np nr np nw
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continue;
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case 0x0504: // MOVE (d16, An), -(An)
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case 0x0604: // MOVE (d8, An, Xn), -(An)
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// np nr np nw
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// n np nr np nw
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continue;
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case 0x0505: // MOVE (d16, An), (d16, An)
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case 0x0605: // MOVE (d8, An, Xn), (d16, An)
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// np nr np nw np
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// n np nr np nw np
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continue;
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case 0x0505: // MOVE (d16, An), (d16, An)
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case 0x0605: // MOVE (d8, An, Xn), (d16, An)
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// np nr np nw np
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// n np nr np nw np
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continue;
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case 0x0506: // MOVE (d16, An), (d8, An, Xn)
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case 0x0606: // MOVE (d8, An, Xn), (d8, An, Xn)
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// np nr n np nw np
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// n np nr n np nw np
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continue;
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case 0x0506: // MOVE (d16, An), (d8, An, Xn)
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case 0x0606: // MOVE (d8, An, Xn), (d8, An, Xn)
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// np nr n np nw np
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// n np nr n np nw np
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continue;
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case 0x0510: // MOVE (d16, An), (xxx).W
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case 0x0610: // MOVE (d8, An, Xn), (xxx).W
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// np nr np nw np
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// n np nr np nw np
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continue;
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case 0x0510: // MOVE (d16, An), (xxx).W
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case 0x0610: // MOVE (d8, An, Xn), (xxx).W
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// np nr np nw np
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// n np nr np nw np
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continue;
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case 0x0511: // MOVE (d16, An), (xxx).L
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case 0x0611: // MOVE (d8, An, Xn), (xxx).L
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// np nr np nw np np
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// n np nr np nw np np
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continue;
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case 0x0511: // MOVE (d16, An), (xxx).L
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case 0x0611: // MOVE (d8, An, Xn), (xxx).L
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// np nr np nw np np
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// n np nr np nw np np
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continue;
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#undef action_calc
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#undef prefix
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//
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// Source = (xxx).W
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//
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//
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// Source = (xxx).W
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//
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case 0x1001: // MOVEA (xxx).W, An
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operation = Operation::MOVEAw;
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case 0x1000: // MOVE (xxx).W, Dn
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op(
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int(MicroOp::Action::AssembleWordFromPrefetch) | MicroOp::SourceMask,
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seq("np nr np", { &storage_.effective_address_[0] }, !is_byte_access));
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op(Action::PerformOperation);
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break;
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case 0x1001: // MOVEA (xxx).W, An
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operation = Operation::MOVEAw;
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case 0x1000: // MOVE (xxx).W, Dn
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op(
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int(MicroOp::Action::AssembleWordFromPrefetch) | MicroOp::SourceMask,
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seq("np nr np", { &storage_.effective_address_[0] }, !is_byte_access));
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op(Action::PerformOperation);
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break;
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case 0x1002: // MOVE (xxx).W, (An)
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case 0x1003: // MOVE (xxx).W, (An)+
|
||||
// np nr nw np
|
||||
continue;
|
||||
case 0x1002: // MOVE (xxx).W, (An)
|
||||
case 0x1003: // MOVE (xxx).W, (An)+
|
||||
// np nr nw np
|
||||
continue;
|
||||
|
||||
case 0x1004: // MOVE (xxx).W, -(An)
|
||||
// np nr np nw
|
||||
continue;
|
||||
case 0x1004: // MOVE (xxx).W, -(An)
|
||||
// np nr np nw
|
||||
continue;
|
||||
|
||||
case 0x1005: // MOVE (xxx).W, (d16, An)
|
||||
// np nr np nw np
|
||||
continue;
|
||||
case 0x1005: // MOVE (xxx).W, (d16, An)
|
||||
// np nr np nw np
|
||||
continue;
|
||||
|
||||
case 0x1006: // MOVE (xxx).W, (d8, An, Xn)
|
||||
// np nr n np nw np
|
||||
continue;
|
||||
case 0x1006: // MOVE (xxx).W, (d8, An, Xn)
|
||||
// np nr n np nw np
|
||||
continue;
|
||||
|
||||
case 0x1010: // MOVE (xxx).W, (xxx).W
|
||||
// np nr np nw np
|
||||
continue;
|
||||
case 0x1010: // MOVE (xxx).W, (xxx).W
|
||||
// np nr np nw np
|
||||
continue;
|
||||
|
||||
case 0x1011: // MOVE (xxx).W, (xxx).L
|
||||
// np nr np nw np np
|
||||
continue;
|
||||
case 0x1011: // MOVE (xxx).W, (xxx).L
|
||||
// np nr np nw np np
|
||||
continue;
|
||||
|
||||
//
|
||||
// Source = (xxx).L
|
||||
//
|
||||
//
|
||||
// Source = (xxx).L
|
||||
//
|
||||
|
||||
case 0x1101: // MOVEA (xxx).W, Dn
|
||||
operation = Operation::MOVEAw;
|
||||
case 0x1100: // MOVE (xxx).W, Dn
|
||||
op(int(MicroOp::Action::AssembleWordFromPrefetch) | MicroOp::SourceMask, seq("np np"));
|
||||
op(Action::PerformOperation, seq("nr np", { &storage_.effective_address_[0] }, !is_byte_access));
|
||||
op();
|
||||
break;
|
||||
case 0x1101: // MOVEA (xxx).W, Dn
|
||||
operation = Operation::MOVEAw;
|
||||
case 0x1100: // MOVE (xxx).W, Dn
|
||||
op(int(MicroOp::Action::AssembleWordFromPrefetch) | MicroOp::SourceMask, seq("np np"));
|
||||
op(Action::PerformOperation, seq("nr np", { &storage_.effective_address_[0] }, !is_byte_access));
|
||||
op();
|
||||
break;
|
||||
|
||||
//
|
||||
// Source = (d16, PC)
|
||||
//
|
||||
//
|
||||
// Source = (d16, PC)
|
||||
//
|
||||
|
||||
case 0x1200: // MOVE (d16, PC), Dn
|
||||
op(int(Action::CalcD16PC) | MicroOp::SourceMask, seq("n np nr np", { &storage_.effective_address_[0] }, !is_byte_access));
|
||||
op(Action::PerformOperation);
|
||||
break;
|
||||
case 0x1200: // MOVE (d16, PC), Dn
|
||||
op(int(Action::CalcD16PC) | MicroOp::SourceMask, seq("n np nr np", { &storage_.effective_address_[0] }, !is_byte_access));
|
||||
op(Action::PerformOperation);
|
||||
break;
|
||||
|
||||
//
|
||||
// Source = (d8, An, Xn)
|
||||
//
|
||||
//
|
||||
// Source = (d8, An, Xn)
|
||||
//
|
||||
|
||||
case 0x1300: // MOVE (d8, An, Xn), Dn
|
||||
op(int(Action::CalcD8PCXn) | MicroOp::SourceMask, seq("n np nr np", { &storage_.effective_address_[0] }, !is_byte_access));
|
||||
op(Action::PerformOperation);
|
||||
break;
|
||||
case 0x1300: // MOVE (d8, An, Xn), Dn
|
||||
op(int(Action::CalcD8PCXn) | MicroOp::SourceMask, seq("n np nr np", { &storage_.effective_address_[0] }, !is_byte_access));
|
||||
op(Action::PerformOperation);
|
||||
break;
|
||||
|
||||
//
|
||||
// Source = #
|
||||
//
|
||||
//
|
||||
// Source = #
|
||||
//
|
||||
|
||||
case 0x1401: // MOVE #, Dn
|
||||
operation = Operation::MOVEAw;
|
||||
case 0x1400: // MOVE #, Dn
|
||||
storage_.instructions[instruction].source = &storage_.prefetch_queue_;
|
||||
op(int(Action::PerformOperation), seq("np np"));
|
||||
op();
|
||||
break;
|
||||
case 0x1401: // MOVE #, Dn
|
||||
operation = Operation::MOVEAw;
|
||||
case 0x1400: // MOVE #, Dn
|
||||
storage_.instructions[instruction].source = &storage_.prefetch_queue_;
|
||||
op(int(Action::PerformOperation), seq("np np"));
|
||||
op();
|
||||
break;
|
||||
|
||||
//
|
||||
// Default
|
||||
//
|
||||
//
|
||||
// Default
|
||||
//
|
||||
|
||||
default:
|
||||
std::cerr << "Unimplemented MOVE " << std::hex << both_modes << " " << instruction << std::endl;
|
||||
// TODO: all other types of mode.
|
||||
continue;
|
||||
}
|
||||
default:
|
||||
std::cerr << "Unimplemented MOVE " << std::hex << both_modes << " " << instruction << std::endl;
|
||||
// TODO: all other types of mode.
|
||||
continue;
|
||||
}
|
||||
} break;
|
||||
|
||||
|
|
|
|||
|
|
@ -129,6 +129,12 @@ class ProcessorStorage {
|
|||
/// Adds 4.
|
||||
Increment4,
|
||||
|
||||
/// Copies whatever is this instruction's source to effective_address_[0].
|
||||
CopySourceToEffectiveAddress,
|
||||
|
||||
/// Copies whatever is this instruction's destination to effective_address_[1].
|
||||
CopyDestinationToEffectiveAddress,
|
||||
|
||||
/// Peeking into the end of the prefetch queue, calculates the proper target of (d16,An) addressing.
|
||||
CalcD16An,
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user