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Starts to make incursions into MOVE[A].l.

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Thomas Harte 2019-03-23 21:03:52 -04:00
parent d7c3d4ce52
commit 43532c8455
2 changed files with 257 additions and 232 deletions
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49
Processors/68000/Implementation/68000Storage.cpp
View File

@ -155,6 +155,12 @@ struct ProcessorStorageConstructor {
step.microcycle.length = HalfCycles(3); step.microcycle.length = HalfCycles(3);
step.microcycle.operation |= (read_full_words ? Microcycle::SelectWord : Microcycle::SelectByte) | (is_read ? Microcycle::Read : 0); step.microcycle.operation |= (read_full_words ? Microcycle::SelectWord : Microcycle::SelectByte) | (is_read ? Microcycle::Read : 0);
if(access_pattern[1] == 'R') {
step.action = Action::IncrementEffectiveAddress0;
}
if(access_pattern[1] == 'W') {
step.action = Action::IncrementEffectiveAddress1;
}
steps.push_back(step); steps.push_back(step);
++address_iterator; ++address_iterator;
@ -357,22 +363,24 @@ struct ProcessorStorageConstructor {
// ... for no reason other than to make the switch below easy to read. // ... for no reason other than to make the switch below easy to read.
const int both_modes = const int both_modes =
((source_mode == 7) ? (0x1000 | (source_register << 8)) : (source_mode << 8)) | ((source_mode == 7) ? (0x1000 | (source_register << 8)) : (source_mode << 8)) |
((destination_mode == 7) ? (0x10 | destination_register) : destination_mode); ((destination_mode == 7) ? (0x10 | destination_register) : destination_mode) |
(is_long_word_access ? 0x10000 : 0);
if(is_long_word_access) {
continue;
} else {
switch(both_modes) { switch(both_modes) {
// //
// Source = Dn or An // Source = Dn or An
// //
case 0x0001: // MOVEA Dn, An case 0x10001: // MOVEA.l Dn, An
case 0x0101: // MOVEA An, An case 0x10101: // MOVEA.l An, An
operation = Operation::MOVEAw; // Substitute MOVEA for MOVE. case 0x00001: // MOVEA.w Dn, An
case 0x0000: // MOVE Dn, Dn case 0x00101: // MOVEA.w An, An
case 0x0100: // MOVE An, Dn operation = is_long_word_access ? Operation::MOVEAl : Operation::MOVEAw; // Substitute MOVEA for MOVE.
case 0x10000: // MOVE.l Dn, Dn
case 0x10100: // MOVE.l An, Dn
case 0x00000: // MOVE.bw Dn, Dn
case 0x00100: // MOVE.bw An, Dn
op(Action::PerformOperation, seq("np")); op(Action::PerformOperation, seq("np"));
op(); op();
break; break;
@ -420,11 +428,11 @@ struct ProcessorStorageConstructor {
// Source = (An) or (An)+ // Source = (An) or (An)+
// //
case 0x0201: // MOVEA (An), An case 0x00201: // MOVEA.w (An), An
case 0x0301: // MOVEA (An)+, An case 0x00301: // MOVEA.w (An)+, An
operation = Operation::MOVEAw; // Substitute MOVEA for MOVE. operation = Operation::MOVEAw;
case 0x0200: // MOVE (An), Dn case 0x00200: // MOVE.bw (An), Dn
case 0x0300: // MOVE (An)+, Dn case 0x00300: // MOVE.bw (An)+, Dn
op(Action::None, seq("nr np", { &storage_.address_[source_register].full }, !is_byte_access)); op(Action::None, seq("nr np", { &storage_.address_[source_register].full }, !is_byte_access));
if(source_mode == 0x3) { if(source_mode == 0x3) {
op(int(is_byte_access ? Action::Increment1 : Action::Increment2) | MicroOp::SourceMask); op(int(is_byte_access ? Action::Increment1 : Action::Increment2) | MicroOp::SourceMask);
@ -432,6 +440,18 @@ struct ProcessorStorageConstructor {
op(Action::PerformOperation); op(Action::PerformOperation);
break; break;
case 0x10201: // MOVEA.l (An), An
case 0x10301: // MOVEA.l (An)+, An
operation = Operation::MOVEAl;
case 0x10200: // MOVE.l (An), Dn
case 0x10300: // MOVE.l (An)+, Dn
op(Action::CopySourceToEffectiveAddress, seq("nR nr np"));
if(source_mode == 0x3) {
op(int(Action::Increment4) | MicroOp::SourceMask);
}
op(Action::PerformOperation);
break;
case 0x0202: // MOVE (An), (An) case 0x0202: // MOVE (An), (An)
case 0x0302: // MOVE (An)+, (An) case 0x0302: // MOVE (An)+, (An)
case 0x0203: // MOVE (An), (An)+ case 0x0203: // MOVE (An), (An)+
@ -647,7 +667,6 @@ struct ProcessorStorageConstructor {
// TODO: all other types of mode. // TODO: all other types of mode.
continue; continue;
} }
}
} break; } break;
default: default:

6
Processors/68000/Implementation/68000Storage.hpp
View File

@ -129,6 +129,12 @@ class ProcessorStorage {
/// Adds 4. /// Adds 4.
Increment4, Increment4,
/// Copies whatever is this instruction's source to effective_address_[0].
CopySourceToEffectiveAddress,
/// Copies whatever is this instruction's destination to effective_address_[1].
CopyDestinationToEffectiveAddress,
/// Peeking into the end of the prefetch queue, calculates the proper target of (d16,An) addressing. /// Peeking into the end of the prefetch queue, calculates the proper target of (d16,An) addressing.
CalcD16An, CalcD16An,