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https://github.com/TomHarte/CLK.git
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Implements ASL, ASR, LSL and LSR.
This commit is contained in:
Thomas Harte
parent
a07de97df4
commit
43f619a081
@ -53,16 +53,16 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
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// TODO: unless an interrupt is pending, or the trap flag is set.
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const uint16_t next_instruction = prefetch_queue_.halves.high.full;
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if(!instructions[next_instruction].micro_operations) {
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decoded_instruction_ = prefetch_queue_.halves.high.full;
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if(!instructions[decoded_instruction_].micro_operations) {
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// TODO: once all instructions are implemnted, this should be an instruction error.
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std::cerr << "68000 Abilities exhausted; can't manage instruction " << std::hex << next_instruction << " from " << (program_counter_.full - 4) << std::endl;
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std::cerr << "68000 Abilities exhausted; can't manage instruction " << std::hex << decoded_instruction_ << " from " << (program_counter_.full - 4) << std::endl;
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return;
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} else {
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std::cout << "Performing " << std::hex << next_instruction << " from " << (program_counter_.full - 4) << std::endl;
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std::cout << "Performing " << std::hex << decoded_instruction_ << " from " << (program_counter_.full - 4) << std::endl;
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}
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active_program_ = &instructions[next_instruction];
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active_program_ = &instructions[decoded_instruction_];
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active_micro_op_ = active_program_->micro_operations;
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}
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@ -523,28 +523,51 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
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overflow_flag_ = (value ^ zero_result_) & m; \
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extend_flag_ = carry_flag_ = value & t;
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#define decode_shift_count() \
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const int shift_count = (decoded_instruction_ & 32) ? data_[(decoded_instruction_ >> 9) & 7].full&63 : (decoded_instruction_ >> 9) & 7; \
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active_step_->microcycle.length = HalfCycles(4 * shift_count);
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#define set_flags_b(t) set_flags(active_program_->destination->halves.low.halves.low, 0x80, t)
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#define set_flags_w(t) set_flags(active_program_->destination->halves.low.full, 0x8000, t)
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#define set_flags_l(t) set_flags(active_program_->destination->full, 0x80000000, t)
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case Operation::LSLm:
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case Operation::ASLm: {
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const auto value = active_program_->destination->halves.low.full;
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active_program_->destination->halves.low.full <<= 1;
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set_flags_w(0x8000);
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} break;
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#define shift_op(name, op, mb, mw, ml) \
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case Operation::name##b: { \
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decode_shift_count(); \
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const auto value = active_program_->destination->halves.low.halves.low; \
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op(active_program_->destination->halves.low.halves.low, shift_count, 0xff, 7); \
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set_flags_b(mb); \
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} break; \
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\
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case Operation::name##w: { \
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decode_shift_count(); \
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const auto value = active_program_->destination->halves.low.full; \
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op(active_program_->destination->halves.low.full, shift_count, 0xffff, 15); \
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set_flags_w(mw); \
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} break; \
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\
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case Operation::name##l: { \
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decode_shift_count(); \
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const auto value = active_program_->destination->full; \
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op(active_program_->destination->full, shift_count, 0xffffffff, 31); \
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set_flags_l(ml); \
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} break; \
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\
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case Operation::name##m: { \
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const auto value = active_program_->destination->halves.low.full; \
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op(active_program_->destination->halves.low.full, 1, 0xffff, 15); \
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set_flags_w(mw); \
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} break;
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case Operation::LSRm: {
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const auto value = active_program_->destination->halves.low.full;
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active_program_->destination->halves.low.full >>= 1;
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set_flags_w(0x0001);
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} break;
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#define lsl(x, c, m, d) x <<= c
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#define lsr(x, c, m, d) x >>= c
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#define asl(x, c, m, d) x <<= c
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#define asr(x, c, m, d) x = (x >> c) | (((value >> d) & 1) * (m ^ (m >> c)))
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case Operation::ASRm: {
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const auto value = active_program_->destination->halves.low.full;
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active_program_->destination->halves.low.full = (active_program_->destination->halves.low.full >> 1) | (value & 0x8000);
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set_flags_w(0x0001);
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} break;
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shift_op(LSL, lsl, 0x80, 0x8000, 0x80000000);
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shift_op(ASL, lsl, 0x80, 0x8000, 0x80000000);
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shift_op(LSR, lsr, 0x01, 0x0001, 0x00000001);
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shift_op(ASR, asr, 0x01, 0x0001, 0x00000001);
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#undef set_flags
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#define set_flags(v, m, t) \
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@ -580,6 +603,7 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
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} break;
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#undef set_flags
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#undef decode_shift_count
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#undef set_flags_b
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#undef set_flags_w
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#undef set_flags_l
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@ -59,6 +59,9 @@ struct ProcessorStorageConstructor {
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* n: no operation for four cycles; data bus is not used;
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* nn: no operation for eight cycles; data bus is not used;
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* r: a 'replaceable'-length no operation; data bus is not used and no guarantees are
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made about the length of the cycle other than that when it reaches the interpreter,
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it is safe to alter the length and leave it altered;
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* np: program fetch; reads from the PC and adds two to it, advancing the prefetch queue;
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* nW: write MSW of something onto the bus;
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* nw: write LSW of something onto the bus;
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@ -121,10 +124,17 @@ struct ProcessorStorageConstructor {
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// Do nothing (possibly twice).
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if(token == "n" || token == "nn") {
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steps.push_back(step);
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if(token.size() == 2) {
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steps.push_back(step);
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step.microcycle.length = HalfCycles(8);
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}
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steps.push_back(step);
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continue;
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}
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// Do nothing, but with a length that definitely won't map it to the other do-nothings.
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if(token == "r"){
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step.microcycle.length = HalfCycles(0);
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steps.push_back(step);
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continue;
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}
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@ -384,45 +394,45 @@ struct ProcessorStorageConstructor {
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{0xffc0, 0x4640, Operation::NOTw, Decoder::CLRNEGNEGXNOT}, // 4-148 (p250)
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{0xffc0, 0x4680, Operation::NOTl, Decoder::CLRNEGNEGXNOT}, // 4-148 (p250)
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{0xf1d8, 0xe000, Operation::ASLb, Decoder::ASLRLSLRROLRROXLRr}, // 4-22 (p126)
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{0xf1d8, 0xe040, Operation::ASLw, Decoder::ASLRLSLRROLRROXLRr}, // 4-22 (p126)
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{0xf1d8, 0xe080, Operation::ASLl, Decoder::ASLRLSLRROLRROXLRr}, // 4-22 (p126)
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{0xffc0, 0xe0c0, Operation::ASLm, Decoder::ASLRLSLRROLRROXLRm}, // 4-22 (p126)
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{0xf1d8, 0xe100, Operation::ASLb, Decoder::ASLRLSLRROLRROXLRr}, // 4-22 (p126)
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{0xf1d8, 0xe140, Operation::ASLw, Decoder::ASLRLSLRROLRROXLRr}, // 4-22 (p126)
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{0xf1d8, 0xe180, Operation::ASLl, Decoder::ASLRLSLRROLRROXLRr}, // 4-22 (p126)
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{0xffc0, 0xe1c0, Operation::ASLm, Decoder::ASLRLSLRROLRROXLRm}, // 4-22 (p126)
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{0xf1d8, 0xe100, Operation::ASRb, Decoder::ASLRLSLRROLRROXLRr}, // 4-22 (p126)
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{0xf1d8, 0xe140, Operation::ASRw, Decoder::ASLRLSLRROLRROXLRr}, // 4-22 (p126)
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{0xf1d8, 0xe180, Operation::ASRl, Decoder::ASLRLSLRROLRROXLRr}, // 4-22 (p126)
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{0xffc0, 0xe1c0, Operation::ASRm, Decoder::ASLRLSLRROLRROXLRm}, // 4-22 (p126)
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{0xf1d8, 0xe000, Operation::ASRb, Decoder::ASLRLSLRROLRROXLRr}, // 4-22 (p126)
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{0xf1d8, 0xe040, Operation::ASRw, Decoder::ASLRLSLRROLRROXLRr}, // 4-22 (p126)
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{0xf1d8, 0xe080, Operation::ASRl, Decoder::ASLRLSLRROLRROXLRr}, // 4-22 (p126)
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{0xffc0, 0xe0c0, Operation::ASRm, Decoder::ASLRLSLRROLRROXLRm}, // 4-22 (p126)
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{0xf1d8, 0xe008, Operation::LSLb, Decoder::ASLRLSLRROLRROXLRr}, // 4-113 (p217)
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{0xf1d8, 0xe048, Operation::LSLw, Decoder::ASLRLSLRROLRROXLRr}, // 4-113 (p217)
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{0xf1d8, 0xe088, Operation::LSLl, Decoder::ASLRLSLRROLRROXLRr}, // 4-113 (p217)
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{0xffc0, 0xe2c0, Operation::LSLm, Decoder::ASLRLSLRROLRROXLRm}, // 4-113 (p217)
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{0xf1d8, 0xe108, Operation::LSLb, Decoder::ASLRLSLRROLRROXLRr}, // 4-113 (p217)
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{0xf1d8, 0xe148, Operation::LSLw, Decoder::ASLRLSLRROLRROXLRr}, // 4-113 (p217)
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{0xf1d8, 0xe188, Operation::LSLl, Decoder::ASLRLSLRROLRROXLRr}, // 4-113 (p217)
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{0xffc0, 0xe3c0, Operation::LSLm, Decoder::ASLRLSLRROLRROXLRm}, // 4-113 (p217)
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{0xf1d8, 0xe108, Operation::LSRb, Decoder::ASLRLSLRROLRROXLRr}, // 4-113 (p217)
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{0xf1d8, 0xe148, Operation::LSRw, Decoder::ASLRLSLRROLRROXLRr}, // 4-113 (p217)
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{0xf1d8, 0xe188, Operation::LSRl, Decoder::ASLRLSLRROLRROXLRr}, // 4-113 (p217)
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{0xffc0, 0xe3c0, Operation::LSRm, Decoder::ASLRLSLRROLRROXLRm}, // 4-113 (p217)
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{0xf1d8, 0xe008, Operation::LSRb, Decoder::ASLRLSLRROLRROXLRr}, // 4-113 (p217)
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{0xf1d8, 0xe048, Operation::LSRw, Decoder::ASLRLSLRROLRROXLRr}, // 4-113 (p217)
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{0xf1d8, 0xe088, Operation::LSRl, Decoder::ASLRLSLRROLRROXLRr}, // 4-113 (p217)
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{0xffc0, 0xe2c0, Operation::LSRm, Decoder::ASLRLSLRROLRROXLRm}, // 4-113 (p217)
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{0xf1d8, 0xe018, Operation::ROLb, Decoder::ASLRLSLRROLRROXLRr}, // 4-160 (p264)
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{0xf1d8, 0xe058, Operation::ROLw, Decoder::ASLRLSLRROLRROXLRr}, // 4-160 (p264)
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{0xf1d8, 0xe098, Operation::ROLl, Decoder::ASLRLSLRROLRROXLRr}, // 4-160 (p264)
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{0xffc0, 0xe6c0, Operation::ROLm, Decoder::ASLRLSLRROLRROXLRm}, // 4-160 (p264)
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{0xf1d8, 0xe118, Operation::ROLb, Decoder::ASLRLSLRROLRROXLRr}, // 4-160 (p264)
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{0xf1d8, 0xe158, Operation::ROLw, Decoder::ASLRLSLRROLRROXLRr}, // 4-160 (p264)
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{0xf1d8, 0xe198, Operation::ROLl, Decoder::ASLRLSLRROLRROXLRr}, // 4-160 (p264)
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{0xffc0, 0xe7c0, Operation::ROLm, Decoder::ASLRLSLRROLRROXLRm}, // 4-160 (p264)
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{0xf1d8, 0xe118, Operation::RORb, Decoder::ASLRLSLRROLRROXLRr}, // 4-160 (p264)
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{0xf1d8, 0xe158, Operation::RORw, Decoder::ASLRLSLRROLRROXLRr}, // 4-160 (p264)
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{0xf1d8, 0xe198, Operation::RORl, Decoder::ASLRLSLRROLRROXLRr}, // 4-160 (p264)
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{0xffc0, 0xe7c0, Operation::RORm, Decoder::ASLRLSLRROLRROXLRm}, // 4-160 (p264)
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{0xf1d8, 0xe018, Operation::RORb, Decoder::ASLRLSLRROLRROXLRr}, // 4-160 (p264)
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{0xf1d8, 0xe058, Operation::RORw, Decoder::ASLRLSLRROLRROXLRr}, // 4-160 (p264)
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{0xf1d8, 0xe098, Operation::RORl, Decoder::ASLRLSLRROLRROXLRr}, // 4-160 (p264)
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{0xffc0, 0xe6c0, Operation::RORm, Decoder::ASLRLSLRROLRROXLRm}, // 4-160 (p264)
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{0xf1d8, 0xe010, Operation::ROXLb, Decoder::ASLRLSLRROLRROXLRr}, // 4-163 (p267)
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{0xf1d8, 0xe050, Operation::ROXLw, Decoder::ASLRLSLRROLRROXLRr}, // 4-163 (p267)
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{0xf1d8, 0xe090, Operation::ROXLl, Decoder::ASLRLSLRROLRROXLRr}, // 4-163 (p267)
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{0xffc0, 0xe4c0, Operation::ROXLm, Decoder::ASLRLSLRROLRROXLRm}, // 4-163 (p267)
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{0xf1d8, 0xe110, Operation::ROXLb, Decoder::ASLRLSLRROLRROXLRr}, // 4-163 (p267)
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{0xf1d8, 0xe150, Operation::ROXLw, Decoder::ASLRLSLRROLRROXLRr}, // 4-163 (p267)
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{0xf1d8, 0xe190, Operation::ROXLl, Decoder::ASLRLSLRROLRROXLRr}, // 4-163 (p267)
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{0xffc0, 0xe5c0, Operation::ROXLm, Decoder::ASLRLSLRROLRROXLRm}, // 4-163 (p267)
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{0xf1d8, 0xe110, Operation::ROXRb, Decoder::ASLRLSLRROLRROXLRr}, // 4-163 (p267)
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{0xf1d8, 0xe150, Operation::ROXRw, Decoder::ASLRLSLRROLRROXLRr}, // 4-163 (p267)
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{0xf1d8, 0xe190, Operation::ROXRl, Decoder::ASLRLSLRROLRROXLRr}, // 4-163 (p267)
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{0xffc0, 0xe5c0, Operation::ROXRm, Decoder::ASLRLSLRROLRROXLRm}, // 4-163 (p267)
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{0xf1d8, 0xe010, Operation::ROXRb, Decoder::ASLRLSLRROLRROXLRr}, // 4-163 (p267)
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{0xf1d8, 0xe050, Operation::ROXRw, Decoder::ASLRLSLRROLRROXLRr}, // 4-163 (p267)
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{0xf1d8, 0xe090, Operation::ROXRl, Decoder::ASLRLSLRROLRROXLRr}, // 4-163 (p267)
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{0xffc0, 0xe4c0, Operation::ROXRm, Decoder::ASLRLSLRROLRROXLRm}, // 4-163 (p267)
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};
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#ifndef NDEBUG
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@ -928,7 +938,9 @@ struct ProcessorStorageConstructor {
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} else {
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op(Action::None, seq("np n"));
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}
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op(Action::PerformOperation);
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// Use a no-op bus cycle that can have its length filled in later.
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op(Action::PerformOperation, seq("r"));
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} break;
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case Decoder::ASLRLSLRROLRROXLRm: {
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@ -282,6 +282,7 @@ class ProcessorStorage {
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Program *active_program_ = nullptr;
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MicroOp *active_micro_op_ = nullptr;
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BusStep *active_step_ = nullptr;
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uint16_t decoded_instruction_;
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/// Copies address_[7] to the proper stack pointer based on current mode.
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void write_back_stack_pointer();
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