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Attempt decoding and disambiguation of Scc, DBcc, Bcc and BSR.
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7d64c4ec66
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@ -198,8 +198,8 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::decode(ui
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//
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//
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// MARK: BTST, BCLR, BCHG, BSET
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// MARK: BTST, BCLR, BCHG, BSET
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//
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//
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// Implicitly: source is a register;
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// b0–b2 and b3–b5: destination effective address;
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// b0–b2 and b3–b5: destination effective address.
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// b9–b11: source data register.
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//
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//
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case OpT(Operation::BTST): case OpT(Operation::BCLR):
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case OpT(Operation::BTST): case OpT(Operation::BCLR):
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case OpT(Operation::BCHG): case OpT(Operation::BSET):
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case OpT(Operation::BCHG): case OpT(Operation::BSET):
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@ -208,11 +208,13 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::decode(ui
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combined_mode(ea_mode, ea_register), ea_register);
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combined_mode(ea_mode, ea_register), ea_register);
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//
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//
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// MARK: STOP, ANDItoCCR, ANDItoSR, EORItoCCR, EORItoSR, ORItoCCR, ORItoSR
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// MARK: STOP, ANDItoCCR, ANDItoSR, EORItoCCR, EORItoSR, ORItoCCR, ORItoSR, Bccl, Bccw, BSRl, BSRw
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//
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//
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// Operand is an immedate; destination/source is implied by the operation.
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// Operand is an immedate; destination/source (if any) is implied by the operation.
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//
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//
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case OpT(Operation::STOP):
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case OpT(Operation::STOP):
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case OpT(Operation::Bccl): case OpT(Operation::Bccw):
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case OpT(Operation::BSRl): case OpT(Operation::BSRw):
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case OpT(Operation::ORItoSR): case OpT(Operation::ORItoCCR):
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case OpT(Operation::ORItoSR): case OpT(Operation::ORItoCCR):
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case OpT(Operation::ANDItoSR): case OpT(Operation::ANDItoCCR):
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case OpT(Operation::ANDItoSR): case OpT(Operation::ANDItoCCR):
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case OpT(Operation::EORItoSR): case OpT(Operation::EORItoCCR):
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case OpT(Operation::EORItoSR): case OpT(Operation::EORItoCCR):
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@ -332,8 +334,9 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::decode(ui
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case OpT(Operation::PEA):
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case OpT(Operation::PEA):
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case OpT(Operation::TAS):
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case OpT(Operation::TAS):
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case OpT(Operation::TSTb): case OpT(Operation::TSTw): case OpT(Operation::TSTl):
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case OpT(Operation::TSTb): case OpT(Operation::TSTw): case OpT(Operation::TSTl):
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case OpT(Operation::Scc):
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return Preinstruction(operation,
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return Preinstruction(operation,
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combined_mode<false, false>(ea_mode, ea_register), ea_register);
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combined_mode(ea_mode, ea_register), ea_register);
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//
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//
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// MARK: UNLINK, MOVEtoUSP, MOVEfromUSP
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// MARK: UNLINK, MOVEtoUSP, MOVEfromUSP
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@ -345,6 +348,17 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::decode(ui
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return Preinstruction(operation,
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return Preinstruction(operation,
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AddressingMode::AddressRegisterDirect, ea_register);
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AddressingMode::AddressRegisterDirect, ea_register);
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//
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// MARK: DBcc
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//
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// b0–b2: a data register.
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// Followed by an immediate value.
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//
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case OpT(Operation::DBcc):
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return Preinstruction(operation,
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AddressingMode::DataRegisterDirect, ea_register,
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AddressingMode::ImmediateData, 0);
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//
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//
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// MARK: MOVEMtoMw, MOVEMtoMl, MOVEMtoRw, MOVEMtoRl
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// MARK: MOVEMtoMw, MOVEMtoMl, MOVEMtoRw, MOVEMtoRl
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//
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//
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@ -364,18 +378,20 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::decode(ui
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// TODO: more validation on the above.
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// TODO: more validation on the above.
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//
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//
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// MARK: TRAP
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// MARK: TRAP, BCCb, BSRb
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//
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//
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// No further operands decoded, but note that one is somewhere in the opcode.
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// No further operands decoded, but note that one is somewhere in the opcode.
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//
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//
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case OpT(Operation::TRAP):
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case OpT(Operation::TRAP):
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case OpT(Operation::Bccb):
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case OpT(Operation::BSRb):
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return Preinstruction(operation,
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return Preinstruction(operation,
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AddressingMode::Quick, 0);
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AddressingMode::Quick, 0);
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//
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//
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// MARK: LINKw
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// MARK: LINKw
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//
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//
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// b0–b2: 'source' address register.
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// b0–b2: 'source' address register;
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// Implicitly: 'destination' is an immediate.
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// Implicitly: 'destination' is an immediate.
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//
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//
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case OpT(Operation::LINKw):
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case OpT(Operation::LINKw):
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@ -383,6 +399,18 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::decode(ui
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AddressingMode::AddressRegisterDirect, ea_register,
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AddressingMode::AddressRegisterDirect, ea_register,
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AddressingMode::ImmediateData, 0);
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AddressingMode::ImmediateData, 0);
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//
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// MARK: ADDQ, SUBQ
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//
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// b0–b2 and b3–5: a destination effective address;
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// b9–b11: an immediate value, embedded in the opcode.
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//
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case ADDQb: case ADDQw: case ADDQl:
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case SUBQb: case SUBQw: case SUBQl:
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return Preinstruction(operation,
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AddressingMode::Quick, 0,
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combined_mode(ea_mode, ea_register), ea_register);
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//
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//
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// MARK: Impossible error case.
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// MARK: Impossible error case.
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//
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//
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@ -390,8 +418,6 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::decode(ui
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// Should be unreachable.
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// Should be unreachable.
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assert(false);
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assert(false);
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}
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}
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// TODO: be willing to mutate Scc into DBcc.
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}
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}
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// MARK: - Page decoders.
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// MARK: - Page decoders.
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@ -623,9 +649,15 @@ Preinstruction Predecoder<model>::decode5(uint16_t instruction) {
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default: break;
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default: break;
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}
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}
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switch(instruction & 0x0c0) {
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switch(instruction & 0x0f8) {
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// 4-173 (p276), though this'll also hit DBcc 4-91 (p195)
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// 4-173 (p276)
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case 0x0c0: Decode(Op::Scc);
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case 0x0c0:
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case 0x0d0:
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case 0x0e0: case 0x0e8:
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case 0x0f0: case 0x0f8: Decode(Op::Scc);
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// 4-91 (p195)
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case 0x0c8: Decode(Op::DBcc);
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default: break;
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default: break;
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}
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}
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@ -636,8 +668,32 @@ template <Model model>
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Preinstruction Predecoder<model>::decode6(uint16_t instruction) {
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Preinstruction Predecoder<model>::decode6(uint16_t instruction) {
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using Op = Operation;
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using Op = Operation;
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// 4-25 (p129), 4-59 (p163) and 4-55 (p159)
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switch(instruction & 0xf00) {
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Decode(Op::Bcc);
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// 4-59 (p163)
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case 1:
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switch(instruction & 0xff) {
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case 0x00: Decode(Op::BSRw);
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case 0xff:
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if constexpr (model != Model::M68000) {
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Decode(Op::BSRl);
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}
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[[fallthrough]];
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default: Decode(Op::BSRb);
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}
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// 4-25 (p129) Bcc
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// 4-55 (p159) BRA (i.e. Bcc with cc = always)
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default:
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switch(instruction & 0xff) {
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case 0x00: Decode(Op::Bccw);
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case 0xff:
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if constexpr (model != Model::M68000) {
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Decode(Op::Bccl);
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}
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[[fallthrough]];
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default: Decode(Op::Bccb);
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}
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}
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}
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}
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template <Model model>
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template <Model model>
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@ -50,11 +50,14 @@ enum class Operation: uint8_t {
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CMPAw, CMPAl,
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CMPAw, CMPAl,
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TSTb, TSTw, TSTl,
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TSTb, TSTw, TSTl,
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JMP, JSR, RTS,
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JMP,
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BRA, Bcc,
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JSR, RTS,
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DBcc,
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DBcc,
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Scc,
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Scc,
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Bccb, Bccl, Bccw,
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BSRb, BSRl, BSRw,
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CLRb, CLRw, CLRl,
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CLRb, CLRw, CLRl,
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NEGXb, NEGXw, NEGXl,
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NEGXb, NEGXw, NEGXl,
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NEGb, NEGw, NEGl,
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NEGb, NEGw, NEGl,
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