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Ensures DBcc properly signals program fetches.

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This commit is contained in:
Thomas Harte 2019-04-21 22:54:20 -04:00
parent 3cb042a49d
commit 44eb4e51ed
3 changed files with 19 additions and 16 deletions
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8
OSBindings/Mac/Clock SignalTests/QLTests.mm
View File

@ -71,20 +71,20 @@ class QL: public CPU::MC68000::BusHandler {
case Microcycle::SelectWord | Microcycle::Read:
cycle.value->full = is_peripheral ? peripheral_result : base[word_address];
if(!(cycle.operation & Microcycle::IsProgram)) printf("[%08x -> %04x] ", *cycle.address, cycle.value->full);
// if(!(cycle.operation & Microcycle::IsProgram)) printf("[%08x -> %04x] ", *cycle.address, cycle.value->full);
break;
case Microcycle::SelectByte | Microcycle::Read:
cycle.value->halves.low = (is_peripheral ? peripheral_result : base[word_address]) >> cycle.byte_shift();
if(!(cycle.operation & Microcycle::IsProgram)) printf("[%08x -> %02x] ", *cycle.address, cycle.value->halves.low);
// if(!(cycle.operation & Microcycle::IsProgram)) printf("[%08x -> %02x] ", *cycle.address, cycle.value->halves.low);
break;
case Microcycle::SelectWord:
assert(!(is_rom && !is_peripheral));
if(!(cycle.operation & Microcycle::IsProgram)) printf("{%04x -> %08x} ", cycle.value->full, *cycle.address);
// if(!(cycle.operation & Microcycle::IsProgram)) printf("{%04x -> %08x} ", cycle.value->full, *cycle.address);
if(!is_peripheral) base[word_address] = cycle.value->full;
break;
case Microcycle::SelectByte:
assert(!(is_rom && !is_peripheral));
if(!(cycle.operation & Microcycle::IsProgram)) printf("{%02x -> %08x} ", cycle.value->halves.low, *cycle.address);
// if(!(cycle.operation & Microcycle::IsProgram)) printf("{%02x -> %08x} ", cycle.value->halves.low, *cycle.address);
if(!is_peripheral) base[word_address] = (cycle.value->halves.low << cycle.byte_shift()) | (base[word_address] & (0xffff ^ cycle.byte_mask()));
break;
}

24
Processors/68000/Implementation/68000Implementation.hpp
View File

@ -56,17 +56,17 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
// should_log |= program_counter_.full >= 0x4F54 && program_counter_.full <= 0x4F84;
// if(should_log) {
std::cout << std::setfill('0');
std::cout << (extend_flag_ ? 'x' : '-') << (negative_flag_ ? 'n' : '-') << (zero_result_ ? '-' : 'z');
std::cout << (overflow_flag_ ? 'v' : '-') << (carry_flag_ ? 'c' : '-') << '\t';
for(int c = 0; c < 8; ++ c) std::cout << "d" << c << ":" << std::setw(8) << data_[c].full << " ";
for(int c = 0; c < 8; ++ c) std::cout << "a" << c << ":" << std::setw(8) << address_[c].full << " ";
if(is_supervisor_) {
std::cout << "usp:" << std::setw(8) << std::setfill('0') << stack_pointers_[0].full << " ";
} else {
std::cout << "ssp:" << std::setw(8) << std::setfill('0') << stack_pointers_[1].full << " ";
}
std::cout << '\n';
// std::cout << std::setfill('0');
// std::cout << (extend_flag_ ? 'x' : '-') << (negative_flag_ ? 'n' : '-') << (zero_result_ ? '-' : 'z');
// std::cout << (overflow_flag_ ? 'v' : '-') << (carry_flag_ ? 'c' : '-') << '\t';
// for(int c = 0; c < 8; ++ c) std::cout << "d" << c << ":" << std::setw(8) << data_[c].full << " ";
// for(int c = 0; c < 8; ++ c) std::cout << "a" << c << ":" << std::setw(8) << address_[c].full << " ";
// if(is_supervisor_) {
// std::cout << "usp:" << std::setw(8) << std::setfill('0') << stack_pointers_[0].full << " ";
// } else {
// std::cout << "ssp:" << std::setw(8) << std::setfill('0') << stack_pointers_[1].full << " ";
// }
// std::cout << '\n';
// }
decoded_instruction_ = prefetch_queue_.halves.high.full;
@ -76,7 +76,7 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
return;
} else {
// if(0x4f7a == program_counter_.full - 4)return;
std::cout << std::hex << (program_counter_.full - 4) << ": " << std::setw(4) << decoded_instruction_ << '\t';
// std::cout << std::hex << (program_counter_.full - 4) << ": " << std::setw(4) << decoded_instruction_ << '\t';
}
active_program_ = &instructions[decoded_instruction_];

3
Processors/68000/Implementation/68000Storage.cpp
View File

@ -3002,6 +3002,7 @@ CPU::MC68000::ProcessorStorage::ProcessorStorage() {
const size_t dbcc_condition_true_offset = constructor.assemble_program("nn np np");
const size_t dbcc_condition_false_no_branch_offset = constructor.assemble_program("n nr np np", { &dbcc_false_address_ });
const size_t dbcc_condition_false_branch_offset = constructor.assemble_program("n np np");
// That nr in dbcc_condition_false_no_branch_offset is to look like an np from the wrong address.
// The reads steps needs to be 32 long-word reads plus an overflow word; the writes just the long words.
// Addresses and data sources/targets will be filled in at runtime, so anything will do here.
@ -3033,6 +3034,8 @@ CPU::MC68000::ProcessorStorage::ProcessorStorage() {
dbcc_condition_true_steps_ = &all_bus_steps_[dbcc_condition_true_offset];
dbcc_condition_false_no_branch_steps_ = &all_bus_steps_[dbcc_condition_false_no_branch_offset];
dbcc_condition_false_no_branch_steps_[1].microcycle.operation |= Microcycle::IsProgram;
dbcc_condition_false_no_branch_steps_[2].microcycle.operation |= Microcycle::IsProgram;
dbcc_condition_false_branch_steps_ = &all_bus_steps_[dbcc_condition_false_branch_offset];
movem_read_steps_ = &all_bus_steps_[movem_read_offset];