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Corrects 68000 address bus during interrupt acknowledge.
All unused bits should be 1, not 0.
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@ -180,7 +180,12 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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// All code below deals only with reads and writes — cycles in which a
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// data select is active. So quit now if this is not the active part of
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// a read or write.
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if(!cycle.data_select_active()) return delay;
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//
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// The 68000 uses 6800-style autovectored interrupts, so the mere act of
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// having set VPA above deals with those given that the generated address
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// for interrupt acknowledge cycles always has all bits set except the
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// lowest explicit address lines.
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if(!cycle.data_select_active() || (cycle.operation & Microcycle::InterruptAcknowledge)) return delay;
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uint16_t *memory_base = nullptr;
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switch(memory_map_[word_address >> 18]) {
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@ -294,17 +299,10 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
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}
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// If control has fallen through to here, the access is either a read from ROM, or a read or write to RAM.
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// TODO: interrupt acknowledge cycles also end up here, which may suggest the 68000 is loading the address bus
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// incorrectly during interrupt acknowledgment cycles. Check.
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switch(cycle.operation & (Microcycle::SelectWord | Microcycle::SelectByte | Microcycle::Read | Microcycle::InterruptAcknowledge)) {
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switch(cycle.operation & (Microcycle::SelectWord | Microcycle::SelectByte | Microcycle::Read)) {
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default:
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break;
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case Microcycle::InterruptAcknowledge | Microcycle::SelectByte:
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// The Macintosh uses autovectored interrupts.
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mc68000_.set_is_peripheral_address(true);
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break;
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case Microcycle::SelectWord | Microcycle::Read:
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cycle.value->full = memory_base[word_address];
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break;
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@ -234,12 +234,6 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
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continue;
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case ExecutionState::BeginInterrupt:
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#ifdef LOG_TRACE
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// should_log = true;
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if(should_log) {
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printf("\n\nInterrupt\n\n");
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}
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#endif
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active_program_ = nullptr;
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active_micro_op_ = interrupt_micro_ops_;
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execution_state_ = ExecutionState::Executing;
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@ -1960,10 +1954,12 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
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// Mutate neessary internal state — effective_address_[0] is exposed
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// on the data bus as the accepted interrupt number during the interrupt
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// acknowledge cycle, with the low bit set since a real 68000 uses the lower
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// data strobe to collect the corresponding vector byte.
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// acknowledge cycle, with all other bits set, including the low bit as
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// a real 68000 uses the lower data strobe to collect the corresponding vector byte.
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//
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// Cf. M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5.1.4.
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accepted_interrupt_level_ = interrupt_level_ = bus_interrupt_level_;
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effective_address_[0].full = 1 | uint32_t(accepted_interrupt_level_ << 1);
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effective_address_[0].full = 0xfffffff1 | uint32_t(accepted_interrupt_level_ << 1);
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// Recede the program counter to where it would have been were there no
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// prefetch; that's where the reading stream should pick up upon RTE.
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