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Merge pull request #1368 from TomHarte/MinorTweaks
Fix trans for instruction fetches.
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commit
47b276ca0b
@ -231,7 +231,7 @@ struct Registers {
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// MARK: - Condition tests.
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/// @returns @c true if @c condition tests as true; @c false otherwise.
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bool test(Condition condition) {
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bool test(Condition condition) const {
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const auto ne = [&]() -> bool {
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return zero_result_;
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};
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@ -549,7 +549,7 @@ class ConcreteMachine:
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uint32_t advance_pipeline(uint32_t pc) {
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uint32_t instruction = 0; // Value should never be used; this avoids a spurious GCC warning.
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const bool did_read = executor_.bus.read(pc, instruction, executor_.registers().mode(), false);
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const bool did_read = executor_.bus.read(pc, instruction, executor_.registers().mode() == InstructionSet::ARM::Mode::User);
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return pipeline_.exchange(
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did_read ? instruction : Pipeline::SWI,
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did_read ? Pipeline::SWISubversion::None : Pipeline::SWISubversion::DataAbort);
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@ -173,7 +173,7 @@ struct MemoryController {
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}
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template <typename IntT>
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bool read(uint32_t address, IntT &source, InstructionSet::ARM::Mode, bool trans) {
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bool read(uint32_t address, IntT &source, bool trans) {
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switch (read_zones_[(address >> 21) & 31]) {
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case Zone::PhysicallyMappedRAM:
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if(trans) return false;
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@ -212,6 +212,11 @@ struct MemoryController {
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return true;
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}
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template <typename IntT>
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bool read(uint32_t address, IntT &source, InstructionSet::ARM::Mode, bool trans) {
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return read(address, source, trans);
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}
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//
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// Expose various IOC-owned things.
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//
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