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Add a catch for the secondary paging register.

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Thomas Harte 2023-01-10 22:24:40 -05:00
parent 520ae7f2b2
commit 483ee8a74f
1 changed files with 20 additions and 0 deletions
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20
Machines/MSX/MSX.cpp
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@ -440,6 +440,11 @@ class ConcreteMachine:
set_use_fast_tape(); set_use_fast_tape();
} }
// For now: support secondary paging on the MSX 2 only.
constexpr static bool supports_secondary_paging() {
return model == Target::Model::MSX2;
}
// MARK: Z80::BusHandler // MARK: Z80::BusHandler
forceinline HalfCycles perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) { forceinline HalfCycles perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) {
// Per the best information I currently have, the MSX inserts an extra cycle into each opcode read, // Per the best information I currently have, the MSX inserts an extra cycle into each opcode read,
@ -524,6 +529,13 @@ class ConcreteMachine:
[[fallthrough]]; [[fallthrough]];
case CPU::Z80::PartialMachineCycle::Read: case CPU::Z80::PartialMachineCycle::Read:
if constexpr (supports_secondary_paging()) {
if(address == 0xffff) {
*cycle.value = paging_.secondary ^ 0xff;;
break;
}
}
if(read_pointers_[address >> 13]) { if(read_pointers_[address >> 13]) {
*cycle.value = read_pointers_[address >> 13][address & 8191]; *cycle.value = read_pointers_[address >> 13][address & 8191];
} else { } else {
@ -534,6 +546,14 @@ class ConcreteMachine:
break; break;
case CPU::Z80::PartialMachineCycle::Write: { case CPU::Z80::PartialMachineCycle::Write: {
if constexpr (supports_secondary_paging()) {
if(address == 0xffff) {
paging_.secondary = *cycle.value;
update_paging();
break;
}
}
write_pointers_[address >> 13][address & 8191] = *cycle.value; write_pointers_[address >> 13][address & 8191] = *cycle.value;
int slot_hit = (paging_.primary >> ((address >> 14) * 2)) & 3; int slot_hit = (paging_.primary >> ((address >> 14) * 2)) & 3;